Input decap in switching regulators

Question

1. In a buck converter, is there any correlation between switching transition time and decoupling capacitor requirement? As per the TI document attached input decap values are only determined by input ripple current and switching frequency.
2. In the text book "A to Z Switching power supplies_Sanjay Maniktla", it was mentioned the noise has little to do with the basic switching frequency of the converter itself — it is the transition that is responsible for most of the noise, and all its attendant problems. Is the author referring to voltage spikes (noise) due to stray inductance alone?

TI document on capacitor selection

Thanks in advance

Answer 1

suppose your swtich handles 1 amp in 10 nanoseconds. the dI/dT = 10^+8 amp/second

Now have a total of 100 nanoHnry inductance in the input loop: the Vin wiring, the Ground wiring, the capacitor wiring, the PCB?, the switch/FET wiring.

What will be the voltage spike?

Vinductor = L * dI/dT

Vinductor = 100nanoHenry * 1 amp / 10 nanoSeconds

Vinductor = 100 / 10 = 10 volts

Have the VDD wiring OVER the Ground plane.

Have the FET drain wiring over the FET source wiring.

You must design the wiring, for minimum enclosed area.