# Calculation for input bulk capacitor of a buck converter: Need help in understanding equations

Below diagram shows the calculation for input bulk capacitor of a buck converter.The bulk capacitor prevents the input voltage from dipping too much during a sudden load change(load step).

Iam struggling to follow the theory behind the derivations followed. I have studied that in a second order RLC circuit, if we apply a step voltage at the input, it takes roughly tr seconds to reflect the change at output (case 1).The rise time equation exactly matches that of in the diagram.

But the present scenario is slighly different from the previous case. A load step (sudden current change) occurs at the output side (Vin side) of RLC circuit (Case 2). This additional load requirement is catered by the host after tr seconds.

Is there any theorem (duality or bidirectional ??) which justifies the usage of the same equation for both cases?

I’m not sure, but maybe we can look at it this way: The (voltage) load step can only drop at the ESR resistor the moment it happens, because the input cap does not allow a fast voltage change. So the ESR ‘sees’ the remaining RLC (+Vhost) in series. So yes, the dynamic response is that of a series RLC circuit.

• Load step means sudden change in current, not voltage Commented Mar 8, 2020 at 11:18
• “The rise time equation...” Which one do you mean. Please specify the [number]. Commented Mar 8, 2020 at 11:24
• Equation 9 and 10 Commented Mar 8, 2020 at 12:47
• [9] seems not correct to me, because BW (bandwidth) depends on resistance R which is not part of the formula. Commented Mar 8, 2020 at 13:36
• It's still not clear if you're talking about a step change in the input voltage Vhost, or a step change in the load (output current). Commented Mar 8, 2020 at 15:49

Yes: reciprocity. Excluding certain conditions, a passive circuit will always have symmetrical response, i.e. s12 = s21.

While the impedances on either side of the LC filter need not be equal (or even finite and nonzero -- one of them can be zero or infinity), for the symmetrical case it will be true that the transfer response (that is, the change in output resulting from some change in input) and the self-impedance response (that is, change in output voltage/current from some change in output current/voltage) will share at least the same time constants; and in well-behaved cases (like a Butterworth filter), the responses will indeed be complementary (e.g. for a 1Ω filter, a 1V step at the input, or 1A step at the output, gives the step response (or its difference from a step) of 1V at the output).

Actually, that's probably still overly general, and, I also haven't specified what kind of "complementary" response that might consist of. But I can afford to be fast and loose in this context, as power supply filter networks are rarely if ever characteristic-impedance matched, and suffer a continuum of source and load impedances, not just one. To deal with this, we typically add resistance of our own, usually lossy capacitors (electrolytics, or others with or without external resistors added in).

In the case where we cannot assume resistive termination, and we insert our own (making an intentionally lossy RLC filter), then we sacrifice the sharpness of a named filter type, while lessening the impact of impedance variation; and by making for example the Q of the filter's poles a maximum of 1 or so, we limit the resonant gain at those frequencies and therefore the transfer and self-impedance response obey they same general rule.

There are still ways to preserve the sharpness of a named filter type (like Butterworth), but it's added expense (e.g., the components required to implement a diplexing filter to give one or both ports a constant-resistance response). Whereas in this context, we really just need some amount of attenuation at EMI/RFI frequencies, very little precision in the cutoff frequency, and we can tolerate significant insertion loss and ripple in the transition band. So the filter tends to be "big enough" and that's that.