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Below diagram shows the calculation for input bulk capacitor of a buck converter.The bulk capacitor prevents the input voltage from dipping too much during a sudden load change(load step).

Iam struggling to follow the theory behind the derivations followed. I have studied that in a second order RLC circuit, if we apply a step voltage at the input, it takes roughly tr seconds to reflect the change at output (case 1).The rise time equation exactly matches that of in the diagram.

But the present scenario is slighly different from the previous case. A load step (sudden current change) occurs at the output side (Vin side) of RLC circuit (Case 2). This additional load requirement is catered by the host after tr seconds.

Is there any theorem (duality or bidirectional ??) which justifies the usage of the same equation for both cases? enter image description here

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I’m not sure, but maybe we can look at it this way: The (voltage) load step can only drop at the ESR resistor the moment it happens, because the input cap does not allow a fast voltage change. So the ESR ‘sees’ the remaining RLC (+Vhost) in series. So yes, the dynamic response is that of a series RLC circuit.

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  • \$\begingroup\$ Load step means sudden change in current, not voltage \$\endgroup\$
    – Divya K.S
    Mar 8 '20 at 11:18
  • \$\begingroup\$ “The rise time equation...” Which one do you mean. Please specify the [number]. \$\endgroup\$ Mar 8 '20 at 11:24
  • \$\begingroup\$ Equation 9 and 10 \$\endgroup\$
    – Divya K.S
    Mar 8 '20 at 12:47
  • \$\begingroup\$ [9] seems not correct to me, because BW (bandwidth) depends on resistance R which is not part of the formula. \$\endgroup\$ Mar 8 '20 at 13:36
  • \$\begingroup\$ It's still not clear if you're talking about a step change in the input voltage Vhost, or a step change in the load (output current). \$\endgroup\$
    – SteveSh
    Mar 8 '20 at 15:49

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