Below diagram shows the calculation for input bulk capacitor of a buck converter.The bulk capacitor prevents the input voltage from dipping too much during a sudden load change(load step).
Iam struggling to follow the theory behind the derivations followed. I have studied that in a second order RLC circuit, if we apply a step voltage at the input, it takes roughly tr seconds to reflect the change at output (case 1).The rise time equation exactly matches that of in the diagram.
But the present scenario is slighly different from the previous case. A load step (sudden current change) occurs at the output side (Vin side) of RLC circuit (Case 2). This additional load requirement is catered by the host after tr seconds.