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If a I2C bus is runs at 400kHz what is the clock period ,data throughput in data-bits/seconds and bus efficiency? i am very new to those buses and is the clock period is 2.5 micro seconds ? any help will be appereciated.

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  • \$\begingroup\$ This sounds like it could be a homework question...I've never heard anyone ask about "bus efficiency" of I2C in the real world. Please tell us what you do understand about I2C and try to answer these questions yourself. \$\endgroup\$ Mar 8, 2020 at 12:19
  • \$\begingroup\$ @ElliotAlderson, "I've never heard anyone ask about "bus efficiency" of I2C in the real world". How have you selected I2C vs other buses for applications, then - guesswork? OP's asked a solid engineering question, nothing to do with homework. \$\endgroup\$
    – TonyM
    Mar 8, 2020 at 12:37
  • \$\begingroup\$ @TonyM The throughput, latency, and efficiency of I2C are so heavily dependent on the particular host and slaves that I don't believe that a question about the intrinsic efficiency of the bus is a practical question. How can you be so certain that this is not a homework question? \$\endgroup\$ Mar 8, 2020 at 13:55
  • \$\begingroup\$ @ElliotAlderson, believe it. Bus efficiency is not system efficiency, you're not understanding comms systems. Re-read the OP's question. On homework, I don't have to be sure. There's no burden on others to disprove an accusation you dreamt up and can't substantiate. Let's present engineering to OPs instead of guesswork. \$\endgroup\$
    – TonyM
    Mar 8, 2020 at 16:53
  • \$\begingroup\$ @TonyM Just to be clear, I did not make any accusation. I said "sounds like" and "could be". \$\endgroup\$ Mar 8, 2020 at 17:34

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There will not be an answer to get you specific throughput numbers without actually knowing what device protocol and operational procedure that you are using. Bus utilization efficiency goes up if you operate with transactions with the device that transfer more data per START / STOP sequence.

From a raw protocol perspective the I2C bus uses 8-bit data size with 9th bit acknowledge. So assuming an SCL clock generated at a uniform rate the raw transfer efficiency will be no better than 8/9 or about 88% efficiency.

To get an idea of how to address this lets take a specific example of a simple serial EEPROM that has an I2C interface and you want to read it two data bytes per transaction. There is some overhead that we could consider as follows:

  1. Start sequence (lets guess at equivalent of 2 clock times).
  2. Slave Address byte to set device select and upper address bits to read. (8 + 1 clocks).
  3. Low address bits of where to read in EEPROM. (8 + 1 clocks)
  4. Repeated Start condition to switch to read mode (guess at equivalent of 2 clock times).
  5. Slave Address Repeat with Read bit set (8 + 1 clocks).
  6. First byte read out (8 + 1 clocks).
  7. Second byte read out (8 + 1 clocks).
  8. Stop sequence (lets guess at equivalent of 2 clock times).
  9. Null time between transactions (Lets guess at 5 clock times).

If you total up all the equivalent clock times above there are 56 of them with a usable 16 clocks of actual utilization to get the data that was being read. This gives a data access efficiency of 16/56 or about 28% efficiency.

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