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I am using SPICE engine (LTSpice) to model a center tapped transformer and then drive its primary side (center tapped) using MOS switches as follows: enter image description here

What I am expecting to see at the output terminals is the amplified square-wave given at the input. However, my output under this configuration is a high voltage peake around 40V and then just flattens. It is possible to get an alternating triangular waveform by changing the inductance values and R2 and R3 but still not even close to what I need to produce. I understand the 0.98 parameter adds a leakage inductance at the primary center tapped side of around 0.01 times Lp1 but do not exactly know where in circuit it resides (schematically). So any answer to following questions is very much appreciated:

  1. is my modelling of "center tapped transformer" in SPICE, an accurate representation of real world transformer? If not, how do I change that?

  2. Assuming the model is correct (or corrected), how can I model this circuit for hand calculations? i.e. from the moment M1 opens, what network should I consider my load to be in series with R2 in order to write differential equations etc for a solution of voltage/current in time domain?

  3. Finally, I understand I may need freewheeling diodes connection in primary side for current escape. Where should I put the diode in primary side?

Any additional insight (considering my intention mentioned above) is also appreciated.

P.S. the input frequency is 1MHz

EDIT1: by choosing: Lp1 = Lp2 = 2.5 uH, Ls1 = 10 uH and transistor component of SI7336ADP, following result is observed: enter image description here

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  • \$\begingroup\$ Leakage resides in series with the 100 ohm resistors but why oh why are you using 100 ohm resistors. You don’t need diodes for the primary because it acts like a see saw with the fulcrum at 5 volts. \$\endgroup\$ – Andy aka Mar 9 '20 at 22:44
  • \$\begingroup\$ @Andy I normally use lower resistances. 100 ohms is just an example. Did you mean I should have used smaller resistance? \$\endgroup\$ – Ams Mar 10 '20 at 7:13
  • \$\begingroup\$ Well, it makes sense. Also, with 100 uH leakage in the secondary it might cause problems with the load at 70 ohm so, maybe you should reduce all inductances by (say) ten and see what happens. Post a picture of your original waveform too to avoid ambiguity and misunderstanding. \$\endgroup\$ – Andy aka Mar 10 '20 at 7:57
  • \$\begingroup\$ @Andyaka I will be adding the waveform as an edit to my question, thank you. \$\endgroup\$ – Ams Mar 10 '20 at 19:06
  • \$\begingroup\$ @Andyaka were you able to have a look at it? I would really appreciate. I could also provide the asc file for LTSpice. \$\endgroup\$ – Ams Mar 11 '20 at 18:10

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