I failed to replicate a simple sample circuit of a N-Channel MOSFET originated in AllAboutCircuit on LTSpice. The current on the load resistor (to mimic the ammeter to measure current on LTSpice) either is in the pic-Amp range (not conducting current, or completely depleted) or in the hundreds of Amp range (the depletion region is enhanced so much?) depending on the polarity of the DC Voltage source (polarity should not matter for MOSFET on Drain and Source). There should not be any voltage difference between the gate and source as both are common out with zero bias voltage.

I have attached below the excerpt from the tutorial and the result I got from LTSpice simulation. Hope someone can help explain what I did wrong and why I am seeing these two drastically different V-I plot. Thank you.

Tutorial vs Simulation


(polarity should not matter for MOSFET on Drain and Source)

It does matter for MOSFET's. Maybe you're mixing up JFET's?

Vto is the same as VGS(th), so, the voltage between Gate and Source.

The upper circuit/simulation
You shorted gate to source, so VGS = 0 V. The default parameter for Vto is 0V.
Therefore, the mosfet is in cut-off mode and the current you see is a 'leakage' current of in pA(1).

When setting Vto correctly to -1V, the overdrive is \$V_{GS} - V_{GS(th)} = 0 - (-1) = 1V\$.

This means for 0V < DC1 < 1V, the mosfet is in triode region, and for DC1 > 1V it is in saturation mode.

For saturation mode applies $$i_D = \frac{1}{2} k_n \left( \frac{W}{L} \right) \left( V_{GS} - V_{GS(th)} \right) $$ where by LTspice default W = L = 100 μm and the transconductance parameter kn is 20 μA/V2.

So, for DC1 > 1V, \$i_D = 1/2 \cdot 20 \text{ } \mu A/V^2 \cdot 1V^2 = 10 \text{ } \mu A \$.

Note that in this case the current is mainly determined by the mosfet, hardly by R1, even when R1 were 1 Ω or 10 Ω.

The lower circuit/simulation
For the lower circuit/simulation the body diode plays the major role because it is forwards biased. This explains why you find huge currents. Current will be about the voltage of DC1 divided by R1.


This 'leakage' current determined by the parameter Gmin, which is the conductance added to every PN junction to aid convergence and has a default value of 1e-12 siemens (1 pS). There are two parallel PN junctions: from drain to bulk and from drain to source, so the combined conductance is 2 pS. This explains the pA.


You need to add this statement:

.model nmos nmos Vto=-1

And then everything will work as expected.

enter image description here

  • \$\begingroup\$ @Huisman This netlist is from the AllAboutCircuit page. Not the OP one as we can see on the left. \$\endgroup\$
    – G36
    Mar 11 '20 at 9:11
  • \$\begingroup\$ You're right! My bad! I'll remove my comment \$\endgroup\$
    – Huisman
    Mar 11 '20 at 9:12

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