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Im using Lattice ECP3 FPGA, didnt found any information about it on the internet. I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface: enter image description here

This Interface latching the ADC data on 24bit bus which compound of the positive edge data (lower bits- 11:0) and negative edge of the data (higher bits- 23:12). my next step is to transfer all this ADC data to FFT block, problem is the FFT need to work on the 12bits data coming from the ADC and not the 24bits, so I need to seperate the data to 2 and send on every rising edge of clock another half of the data, and its important not to lose any sample.

So I already have a working design, I did 2 FIFOs one for the positive edge data and second for the negative edge data, created mux which change its state evey rising edge clock, and when I want to read the data from the FIFOs to the FFT block, I taking one sample from the 1st FIFO and 2nd sample from the 2nd FIFO and so on... I have working synthesis and debuggin:

enter image description here

as you can see the input to the FFT block (dire) gets the adc_data_posedge/negedge_buff as described. but I have strong feeling that this way of implementation is not the right way to make this design. I read that using 2 FIFOs for the same input block could make sync problems and so on..

It could be better if I could take the ADC data bus of 24bits and write to 2 cells of the FIFO at a time in the rising edge of the clock. This way ill create 12bit width FIFO and write to 2 cells at a time and dont need to use 2 FIFOs. there is a possible way to do it?

another way to ask my question is, lets assume you have to design architecture which takes DDR ADC data and store it in the FIFO and then use the FIFO output as input to FFT block. how would you do it?

enter image description here

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    \$\begingroup\$ You need a 2x clock inside your FPGA. Or else convert the DDR data to SDR with a pair of registers (most FPGAs have such registers built into the IOBs), doubling the width, and use a single FIFO that's also twice as wide. \$\endgroup\$
    – Dave Tweed
    Commented Mar 11, 2020 at 11:26
  • \$\begingroup\$ ok thanks but that what I already did. I used Highspeed I/O Interface from Lattice (GDDRX1) which took the 12bit ddr data from the adc and stored it in 24bit bus which I can use now. from here its not a problem to create 24bit width FIFO and store there this date. BUT I need to use the 24bit bus twice per clock cycle because in this 24bit bus stored 2 samples data (12msb bits and 12lsb). How can I do it without using 2x clock? \$\endgroup\$
    – Michael Rahav
    Commented Mar 11, 2020 at 14:33
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    \$\begingroup\$ You can't. You either need an FFT that accepts two samples per clock, or you can only transfer data to the FFT at half the speed of the ADC. \$\endgroup\$
    – Dave Tweed
    Commented Mar 11, 2020 at 14:41
  • \$\begingroup\$ ok thanks. so the waveform I attached in the post is acceptable way to do it from what I understand. (Lattice FFT IP doesnt accept two samples per clock) \$\endgroup\$
    – Michael Rahav
    Commented Mar 11, 2020 at 14:43
  • \$\begingroup\$ No, not if I correctly understand what you're doing. You appear to be creating another DDR stream at the output of the FIFOs, which surely won't be compatible with your FFT unless it has a 2x clock. What exactly does "I already have a working design" mean? \$\endgroup\$
    – Dave Tweed
    Commented Mar 11, 2020 at 14:46

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My first inclination would be to sync two FIFOs, each working on a different clock edge, and add additional circuitry to ensure they stay in sync. A second approach would be to XOR the clock signal with a delayed version of itself, essentially generating a pulse on each clock edge. However, if you don't have a faster clock available, it's going to be an asynchronous delay, so you have to make sure you satisfy your setup and hold times across all conditions.

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