I'm creating board which is supposed to withstand OV/UV and reverse voltage. I've chosen LTC4365CTS8#TRMPBF(datasheet) IC to deal with this problem. In reference schematic for 24V input they are using dual N-ch mosfet that has max G-S voltage of 20V(SI9945 datasheet). What exactly does max G-S voltage mean and when is it applicable? Is this some kind of error in the datasheet or is my understanding of it incorrent? 
thanks in advance
G-S voltage is the voltage from the gate to the source. In this case, when on, Vs=Vin, and when off, it's close to zero due to the body diodes (not shown above) bleeding charge off to Vout. Vg will be a few volts above Vs when on, and probably zero or undriven when off. The Vds is a larger concern here, but that's rated at 60V.
Mosfet gates have an oxide layer that is very thin and hence fragile .The gate capacitance is relatively high .If there was a voltage breakdown between gate and source due to excess volts the stored energy in the capacitance can be enough to destroy the device .The 20 Volt gate source rating of your fet is quite normal.Lower threshold devices intended for easy microprocessor interface tend to have lower gate source voltage ratings because the gate oxide layer is thinner .Your circuit diagram is an app note which can show the chip working for demo purposes .Most designers zener clamp their mosfet gates for production .Remember that a high voltage fet as in high drain source volts has a low gate source voltage rating .
