I'm thinking about the trace/lane ordering to 167Mhz SDRAM with 4-layer PCB:
Now its follow:
- Data traces
- CLK (only)
- DQM traces
- Address + control + command (Ax + BAx + Strobes and CKE)
Is it better if the DQM traces will be placed to 1 or 4 layer? This contains four datalanes and four banks.
Manufacturer recommend to keep the Data off from Address/Control group layer, but if the Data group contain one DQM, is the DQM actually "control" or "data"?
Any other suggestions to layout would be very welcome.