I'm thinking about the trace/lane ordering to 167Mhz SDRAM with 4-layer PCB:

Now its follow:

  1. Data traces
  2. CLK (only)
  3. DQM traces
  4. Address + control + command (Ax + BAx + Strobes and CKE)

Is it better if the DQM traces will be placed to 1 or 4 layer? This contains four datalanes and four banks.

Manufacturer recommend to keep the Data off from Address/Control group layer, but if the Data group contain one DQM, is the DQM actually "control" or "data"?

Any other suggestions to layout would be very welcome.

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  • \$\begingroup\$ Are the 1. to 4. bullet points to list the 4 layers of your PCB? I think it'd be really hard to keep a ground reference for all your signals if they spread on all 4 layers, you could stagger them from one to the other, does not seem ideal. If you have no other choice because of space constraint, you may want to consider adding 2 more layers for your ground references \$\endgroup\$ – eeintech Mar 12 at 18:13
  • \$\begingroup\$ Better to route DQ and DQS together, DQS is intended to track the DQ timings, I would tend to add DQM with these too. \$\endgroup\$ – Brian Drummond Mar 12 at 18:34

The challenge with 4 layers is to maintain a good reference plane if you have to change layers. It's not impossible, but it takes planning.

Generally, use this stackup:

  • L1: Signal
  • L2: GND
  • L3: Power
  • L4: Signal

Try to route on L1 as much as possible. If you have to change planes, place a bypass cap near the signal via where the plane change takes place. This provides an AC return path for your signal.

DQ / DQM and DQS are the fussiest. Give them priority in routing, and use as few layer changes as you can (preferably 0, no more than 1.) CLK and address/control will generally route together.

That all said, you say '4 banks' - did you mean ranks? That is, 32-bit wide x 4 sets of chips? If your board is that big, do not consider 4 layers at all, the signal integrity issues will be all but impossible to surmount.

This may be useful to you: DDR bus design review

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  • \$\begingroup\$ No I meant 4 banks (4M x 32 x 4 banks) in single 90 pad bga package. The memory is 2x oversized (512 Mb), because I did not found other appropriate product. The MCU capability to drive is 256 Mb. Purpose is only to learn (and get workable solution). I'm doing this design with Kicad, so parallel tools are as almost none. In following picture the SDRAM fanout, purple(L3) is the DQMx and the red(L1) ones wich end to via is VCC or GND. Yellow(L2) = CLK. Others commented. I will change the DQM and CLK layers and will try to route. !fanout \$\endgroup\$ – Jdoe Mar 12 at 21:54
  • \$\begingroup\$ Ok, one chip (one rank). Should be straightforward then. \$\endgroup\$ – hacktastical Mar 12 at 22:00

Data lines can be swapped to ease routing, as long as bytes groups are respected :

  • You can swap D0 and D2,

  • You can swap D[7:0] with D[15:8], but corresponding DQM signals must be swapped as well.

  • Adresses can sometimes be swapped, but some specific bits are used during initialisation, different order is not always compatible with the SDRAM controller used.

(well, it can seem obvious,...)

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