I am trying to understand how the main crystal on a (very) old IBM MDA videocard, running at 16.257 MHz is being divided into lower frequencies like the 1.80633 MHz that its main display controller chip (MC6845) expects as a clock.
As you can see from the schema below, something needs to convert the 16.257 MHz clock from the crystal down to a 1.80633 MHz character clock that is fed into the display controller (the display controller chip will then calculate the hsync / vsync / .....). So focus here is on how to get from 16.257 MHz to 1.80633 MHz
There are lots of logic gates in the circuit, and although I have found the schemas for the card online I am lacking some understanding on how to interpret what is going on.
I've been told that the 74LS174 (U1) is responsible for that, and I am indeed seeing both the 16.257 MHz (pin 9), and the 1.80633 MHz (pin 3) when using my multimeter, but I don't understand how it is doing the actual division.
I know that in the circuit 5 D-type flip flops in the 74LS174 are being used, where each output is fed back into the next flip flop input, but I don't understand how it works especially the 3.612 MHz ( = 16.257 / 4.5) I am seeing on all output pins and the 1.80933 MHz on the first flip flop input pin (pin 3). For that input some kind of feedback loop is used involving an LS32 and LS10.
Does this construct have a name, and how can I go about understand more on the inner workings of this thing.