0
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Everytime i run modelsim altera i get the output with 'z' in it and i dont know what is causing this.

Modules:

module orgate(
                input [3:0] a1,
                input [3:0] b1,
                output [3:0] w1
                );

assign w1 = a1 | b1;

endmodule 

module xorgate(
                input [3:0] a2,
                input [3:0] b2,
                output [3:0] w2
                );

assign w2 = a2 ^ b2;

endmodule 

module comparator(
                input [3:0] a3,
                input [3:0] b3,
                output reg [3:0] w3
                );

always@(*)
begin

if( (a3^b3) == 0 )
w3<=1;
else
w3<=0;


end

endmodule 

module sumator(
                input [3:0] a4,
                input [3:0] b4,
                output [3:0] w4
                );

assign w4 = a4 + b4;

endmodule

module mux4(
                input [3:0] in1,
                input [3:0] in2,
                input [3:0] in3,
                input [3:0] in4,
                input [1:0] sel,
                output reg [3:0] out_mux
                );

always@(*)
begin 

case(sel)

0: begin out_mux = in4;end
1: begin out_mux = in3;end
2: begin out_mux = in2;end
3: begin out_mux = in1;end

endcase

end

endmodule 

Top module:

module top(
                input [3:0] a_top,
                input [3:0] b_top,
                input [1:0] sel_top,
                output [3:0] out_top
                );

wire w1_t,w2_t,w3_t,w4_t;

orgate P1(
            .a1(a_top),
            .b1(b_top),
            .w1(w1_t)
            );

xorgate P2(
            .a2(a_top),
            .b2(b_top),
            .w2(w2_t)
            );

comparator P3(
            .a3(a_top),
            .b3(b_top),
            .w3(w3_t)
            );

sumator P4(
            .a4(a_top),
            .b4(b_top),
            .w4(w4_t)
            );

mux4 P5(
            .in1(w1_t),
            .in2(w2_t),
            .in3(w3_t),
            .in4(w4_t),
            .sel(sel_top),
            .out_mux(out_top)
            );

endmodule 

Tb module:

module circuit_tb();

reg [3:0] a_tb;
reg [3:0] b_tb;
reg [1:0] sel_tb;
wire [3:0] out_tb;

top T(
        .a_top(a_tb),
        .b_top(b_tb),
        .sel_top(sel_tb),
        .out_top(out_tb)
        );

initial begin

a_tb=5;
b_tb=13;
sel_tb=0;
#100

a_tb=9;
b_tb=13;
sel_tb=3;
#100

a_tb=9;
b_tb=4;
sel_tb=2;
#100

a_tb=9;
b_tb=15;
sel_tb=1;
#100

a_tb=15;
b_tb=15;
sel_tb=1;
#100

$stop;

end


endmodule

The waveform

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4
  • \$\begingroup\$ Need waveforms and the source code for all of your modules, not just the top level. \$\endgroup\$ Mar 14, 2020 at 19:09
  • \$\begingroup\$ Z's on outputs usually mean there is nothing driving it. \$\endgroup\$
    – dave_59
    Mar 14, 2020 at 19:32
  • \$\begingroup\$ In most (beginners) cases 'z' means you have defined a wire and not assigned a value or not connected the signal to a driving output. I have seen numerous questions about this where the user was looking at the signal at the wrong level in the simulation (mostly: looking at the top level (unconnected) signals, whilst driving signals with exact the same names lower in the hierarchy) \$\endgroup\$
    – Oldfart
    Mar 14, 2020 at 19:34
  • \$\begingroup\$ I edited the post, i hope it helps \$\endgroup\$ Mar 14, 2020 at 19:39

1 Answer 1

1
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All your ports are 4 bit wide but your wires are only 1 bit wide:

wire w1_t,w2_t,w3_t,w4_t;

Thus only the LS bit gets through and that one is not 'z'.

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