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I have a parallel EEPROM chip (AT28C256 to be precise). I keep the OE and CE lines low. Some address is set at the address bus. What happens on the data bus when I flip one address bit?

  • Does it switch instantly from the old data value to the new data value, all bits at once?
  • Does switch bit-by-bit (some bits sooner, some bits later)?
  • Does it go through some random intermediate state?
  • Does it go through High-Z?
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  • \$\begingroup\$ Well it probably is not the last one. For the rest it all depends how the internal hardware works (banks, muxes, decoders etc.) so nobody can tell except the designer. \$\endgroup\$
    – Oldfart
    Commented Mar 14, 2020 at 20:28
  • \$\begingroup\$ I'd go with option 3 seeing as it's compatible with all the other options. don't rely on any behaviour that's not specified in the datasheet. \$\endgroup\$ Commented Mar 15, 2020 at 2:23

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tl; dr version: If you were counting on the EPROM outputs for asynchronous logic, that’s a very bad idea.

The EPROM data bits change more or less at the same time after some delay from address stable. Emphasis on that weasel-phase, more or less. Strictly speaking, there is a period of unknown data state as the EPROM logic propagates the address through decoding, reading, then output.

This period of unknown data is the access time. There is no guarantee that the data will change only once after an address change. It could glitch through multiple states before it settles down.

The safer way to use EPROM output as logic would be to register it (use a clock to capture the output).

On the other hand, if you require an asynchronous, glitch-free output for logic, consider a programmable logic device instead.

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    \$\begingroup\$ There is no guarantee that the bits will change monotonically from the initial state to the final state, they may change multiple times before they settle. It is not wise to use them directly into a clock input of another device. They can be used as a clock enable provided they are not sampled until after the guaranteed setting time. \$\endgroup\$ Commented Mar 14, 2020 at 21:33
  • \$\begingroup\$ Yep. That is what a PLA is for. \$\endgroup\$ Commented Mar 14, 2020 at 21:37
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The only thing that the manufacturer guarantees is that the data is valid Tacc (address access time) ns after the address bus is stable. According to the data sheet, this is anywhere from 150 ns (max) to 350 ns (max), depending on the speed grade part you're using.

Anything other than that I cannot say. You're asking for trouble in my opinion if your design is counting on "instantaneous" or "monotonic" or some other un-specified behavior of the data outputs.

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