I'm making a circuit board with Ethernet (PoE if that makes a difference) coming in through an M12 connector, passing through magnetics and a PHY and going to a micro. I've always heard that there are two things to be avoided when routing high-speed signals: vias because they mess with impedance (which I've matched pretty closely to 100 Ohms) and routing on the top/bottom layers because EMI/EMC.

I've already had to use some vias when routing from the M12 connector to the magnetics due to pin layout, but the stretch from the magnetics to the PHY is currently on the top layer only. I'll only be using 10/100 speeds, the routed length is about 20mm, there can/will be a ground plane underneath the signal, everything is length-matched.

Which is the greater evil? Having vias or routing on the top/bottom layers? Does it matter at all at that speed/trace length?

Here is the original layout:

M12 connector, magnetics, RMII PHY

Here is the layout after rerouting the input to eliminate vias. Since only 2 pairs are used in 10/100, I didn't bother with length matching/single-layer routing for the other two:

enter image description here

  • \$\begingroup\$ Can you share your layout? Can you avoid vias by swapping pins on the magnetics? But in the end the likely answer is (c) it doesn't matter at 100 Mpbps. \$\endgroup\$
    – The Photon
    Commented Mar 15, 2020 at 20:39
  • \$\begingroup\$ @ThePhoton added snip - looking at it, I can possibly avoid the vias on the input with some longer traces/pin swapping. I'll also move those larger power traces from the PoE so they don't run directly under the signal \$\endgroup\$ Commented Mar 15, 2020 at 21:12
  • \$\begingroup\$ I'd be more worried about routing the isolated ethernet signals and the POE signals over local ground plane. Usually if there is a ground plane under the traces between the transformer and the connector, it is not connected to local ground but capacitively to chassis ground. \$\endgroup\$
    – Justme
    Commented Mar 15, 2020 at 21:23
  • \$\begingroup\$ @Justme my understanding of what is required in terms of a reference/ground plane isn't amazing, but I was wondering about the isolation, given the PoE needs to be something like 1500V isolated. Can I get away without having any plane under those traces, or with a large pour that isn't actually connected to anything? \$\endgroup\$ Commented Mar 15, 2020 at 21:27
  • \$\begingroup\$ What PHY chip it is? What transformer is it? Did you look for reference designs with them? They can help with the design. I think you are also missing the AC coupled Bob Smith termination for the pairs. And the vias on topmost pair are asymmetric, it is best if they have same electrical distance so signal hits both vias simultaneously. Having said that, 100M ethernet should be easy, as there are completely separate RX and TX pairs, their lengths (in my opinion) do not need to be matched. The POE power also don't care about whether all pairs are matched or not. Gigabit and HDBaseT are harder. \$\endgroup\$
    – Justme
    Commented Mar 15, 2020 at 22:19

1 Answer 1


Let's start from the basics. You do not want vias on your high speed signals because

(1) vias can go through ground and power planes so your 2d impedance geometry calculations now become 3d impedance geometry calculations.

(2) all your signals need a return path. So if you insert two vias on a differential path you also need to insert two grounding vias

Check rule 6 from this memo: https://www.autodesk.com/products/eagle/blog/8-pcb-grounding-rules/

Also if this is a group project you do not want everyone to blame you for all the problems. It will be harder for you to convince yourself/your_team that this issues do not come from a mismatch via than from exterior layer noice. Because you can buy a "shield box" that can prove that the noisy measuments do come from noise.

So forget about the routing vías and do the top/bottom layer option. Also it will help if you place some shielding vias (you might need to ask manufacturer for some specs for you via) https://www.altium.com/documentation/altium-designer/via-stitching-and-via-shielding-ad.

As for the PoE, it does sound like it is going to give you some issues if your traces are <10mils apart. Consult the manufacturer for the voltage/current you want.

  • \$\begingroup\$ I'm not sure rule 6 applies here since it's a differential signal, isolated from gnd \$\endgroup\$ Commented Mar 16, 2020 at 19:16

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