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In an NMOS, does current flow from source to drain or vice-versa?

This Wikipedia page is confusing me: http://en.wikipedia.org/wiki/MOSFET

Image that's confusing me

The above image confuses me. For the N-channel, it shows the diode's polarity going towards source in some, but away from the source in others.

I'm wondering which terminal should be connected to the power source (i.e. the positive battery terminal) and which should be connected to the power user (i.e. electric motor).

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  • \$\begingroup\$ BTW, I have looked at other questions, but all are very confusing for me (I'm in High School). \$\endgroup\$ – PitaJ Nov 11 '12 at 3:50
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Conventional current flows from Drain to Source in an N Channel MOSFET.
The arrow shows body diode direction in a MOSFET with a parsitic diode between source and drain via the substrate. This diode is missing in silicon on saphire.

2a is a JFet so different topology.

2d is a MOSFET with no body diode. I've never seen one

\2e is a depletion mode FET - it is on with no gate voltage and takes negative voltage to turn the FET off. So diode has other polarity otherwise body diode would conduct whenever there was gate voltage.

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  • \$\begingroup\$ Typically you use 2d (even better, without arrow, as the source/drain is determined by the voltage, and not a priori) in digital circuits. The bulk, in fact, is typically connected to the rail (VCC or GND, depending on the MOSFET polarity). But yes, there exists "MOSFETs" without body diode: thin-film-transistors (either organic or inorganic) are an example. \$\endgroup\$ – next-hack Oct 15 '17 at 7:25
  • \$\begingroup\$ @next-hack (2) Yes. Also insulating substrate devices such as Silicon on Saphire. (1) I dislike the arrow-less symbol. Your "... determined by the voltage ..." comment is somewhat ambiguous (not wrong per se - just of uncertain meaning here.) A given physical device is always a P or N channel and the source and the identity of the three terminal does not change. The channel is enhanced in 2 quadrants by Vgs so in eg an N channel current flow may be D to S or S to D BUT Vgs must always be positive to turn the device on. I know you know this but I read your comment as suggesting otherwise. \$\endgroup\$ – Russell McMahon Oct 16 '17 at 3:47
  • \$\begingroup\$ Yes, sorry, I was referring to planar MOSFETs in ICs, where they are symmetric, and they are drawn as a 3 terminal devices, because the substrate is connected to VDD (pMOSFETs) or GND (nMOSFETs). \$\endgroup\$ – next-hack Oct 16 '17 at 5:12
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When a channel exists in a MOSFET, current can flow from drain to source or from source to drain - it's a function of how the device is connected in the circuit. The conduction channel has no intrinsic polarity - it's kind of like a resistor in that regard.

The intrinsic body diode inside the MOSFET is in parallel with the conduction channel, however. When the conduction channel is present, the diode is shunted and current flows through the path of least resistance (the channel). When the channel is off, the diode is in circuit and will either conduct or block depending on the drain-source current polarity.

As your picture shows, there are both N-channel and P-channel devices, as well as enhancement mode and depletion mode devices. In all of these cases, current can flow from source to drain as well as from drain to source - it's just a matter of how the device is connected in the circuit.

Your picture does not show the intrinsic diode in the devices - the arrow point towards or away from the gate is an indication of the channel type (N-channel points towards the gate, P-channel points away from the gate).

n-channel enhancement MOSFET

This symbol shows you the inherent diode between drain and source.

N-channel enhancement devices need a voltage on the gate higher than the source in order to create a conduction channel. (Enhancement devices don't have a channel automatically, and need gate voltage to create one - because it's N-channel \$V_{gate} > V_{source}\$ for this to happen.)

P-channel enhancement devices need a voltage on the gate lower than the source in order to create a conduction channel. (Enhancement devices don't have a channel automatically, and need gate voltage to create one - because it's P-channel \$V_{gate} < V_{source}\$ for this to happen.)

N-channel delpetion devices have a channel by default, and need a voltage on the gate lower than the source in order to turn the channel off. The channel can be widened to a certain extent by increasing the gate-to-source voltage above 0.

P-channel depletion devices also have a channel by default, and need a voltage on the gate higher than the source in order to turn the channel off. The channel can be widened to a certain extent by decreasing the gate-to-source voltage below 0.

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    \$\begingroup\$ I wish the wikipedia article was this clear. \$\endgroup\$ – Timmmm Jan 21 '15 at 11:12
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    \$\begingroup\$ Great answer, thank you. I think the answer will benefit if you also explain what the diode is for. Assuming there is a simple explanation, of course. \$\endgroup\$ – Violet Giraffe Jan 24 '16 at 17:08
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    \$\begingroup\$ @VioletGiraffe It isn't for anything, really. It's just a consequence of the physical construction of the part. Some savvy designs do make use of it, and some manufacturers spec out its performance as well. \$\endgroup\$ – Adam Lawrence Oct 19 '17 at 18:47
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I haven't taken any semiconductor classes, but if you're interested in an answer constrained to circuit-level operation, the quick answer is:

with NMOS, current flows from Drain-to-source (arrow points away from device at the Source) with PMOS, current flows from Source-to-drain (arrow points to the device at the Source)

In the diagram above, the words P-channel refer to the type of channel that forms underneath the Gate. The P signifies that the channel forms on P-type semiconductor, while the N signifies an N-type semiconductor.

With respect to the confusion. you're right, it is confusing. What you're seeing is known as a source-body tied terminal. In some applications this is useful (see below for more.) Ignore it for the time being.

Generally, when examining an analog circuit schematic, it is conventional to see arrows on the Source terminal of the transistor.

When examining digital transistor-level schematics (as opposed to gate-level, i.e. AND, OR, XOR gates), conventionally, there are no arrows. The distinguishing aspect is that the PMOS will have a little bubble at the Gate terminal, while the NMOS won't have any bubble. Be assured, they are in fact the same transistors (both PMOS and NMOS) in both analog and digital applications. But the way they are operated is very different.

Fun Fact for a beginner The transistor is a four-terminal device: Gate, Drain, Source, and Body. As an introduction to microelectronics, it is conventional to ignore the body terminal intially, but only to assist in familiarizing you with the main equations. However there is a semiconductor phenomenon known as the body-effect which introduces an added layer of complexity to hand calculations with respect to calculating the quiescent operating point of a transistor (quiescent operating point is an important word you'll encounter; it's just a fancy word that signifies the IV or current-voltage operating point of the transistor in question.)

Modeling a transistor is highly complex undertaking and is an electrical engineering or applied physics discipline in itself. Any introductory textbook in microelectronics usually starts a chapter mentioning p-n junctions (a type of doped silicon semiconductor).

If you're really interested, and have a basic grasp of quadratic equations and algebra, you may want to take a look at a great introductory textbook written by Behzad Razavi. I wish I had this book when I took microelectronics in university. However it assumes an understanding of Basic Circuits (i.e. resistors, capacitors, and inductors.)

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    \$\begingroup\$ Understanding how to model a FET with maximum accuracy may require a university course or equivalent. But understanding the basic model and how to use it in a circuit is something most hobbyists should be able to do. \$\endgroup\$ – The Photon Nov 11 '12 at 5:31
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Yes, the current can flow from drain to source and vice-versa. To simplify it even further, I would like to add a bit to just what @Adam Lawrence has mentioned.

I am sure you are familiar with the cross section of the CMOS transistor. You can see that the cross section of the Mosfet is EVEN from the center vertical line. So, whichever (out of the two terminals on sides of nmos) terminal has higher voltage than the other terminal, that becomes your drain (for NMOS) and the other terminal with lower voltage becomes the source (for nmos). The reverse is followed for pmos.

Nevertheless, be careful when buying/dealing with discrete 3 pin Mosfets (i.e SiHG47N60EF) where internal bulk is already connected to the source(for nmos) or to the drain (for pmos) internally. This makes the mosfet pins predefine as mentioned in the datasheet. In that case, the above is still true that higher voltage terminal is drain and lower voltage terminal is source for nmos. However, if you apply higher voltage to the predefined source as mentioned in the datasheet, the threshold voltages will not be same as mentioned in datasheet. And your transistor will not behave as same as what is specified in the datasheet.

enter image description here

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    \$\begingroup\$ But this switching based on voltage wouldn't work in most actual transistors because they are diodic, right? \$\endgroup\$ – PitaJ Sep 16 '15 at 23:11
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    \$\begingroup\$ Yes they are. Those diodic mosfets are referred to as reverse body diode which have slightly different structure from the one above and you are right, they won't work if you swap drain and source pins. The picture above depicts the mosfet usually referred to in an integrated chip i.e VLSI designs. \$\endgroup\$ – dr3patel Sep 16 '15 at 23:51
  • \$\begingroup\$ The picture shows the kind of MOSFET that is used in integrated circuits since it allows the source and drain connections of every transistor to be separate, at the expense of connecting every transistor's substrate and the more significant expense of requiring that all source, gate, and drain connections be made on the same side of the die. \$\endgroup\$ – supercat May 26 '17 at 21:09

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