Which clock path did you intend to select? These modern MCUs have a zillion options.
I believe that this is the default path (in red).
32768/25 = 1310 Hz
Toggling at 1310 Hz yields 655 Hz. Not exactly what you are seeing, but you get the idea. You need to verify that every mux and divider is set appropriately along the intended path.
Edit: I have a MSP430FR5994 (similar to your MCU, they share the same user's guide) running on my bench, so I can easily test your software. I get 722 Hz. I know that if you use an interrupt, the count is exact. You are polling, which could still work depending on how you poll and clear. I don't see the minor discrepancy yet.
Also, if you are going to use the LF oscillator, check to see if Q1 is installed. The schematic leads me to believe that it is optional, but TI sometimes changes little details from rev to rev.
http://www.ti.com/lit/ug/slau367o/slau367o.pdf - figure 3-1
Edit2: Thanks to the tip from CL, I finally have something working. It doesn't do what you expect, since it uses LFXT. Depending on how accurate you need 5 mS, you may not be able to use LFXT.
It produces 32786/25/2 = 655 Hz.
If you are trying something new, always start with a known good code example. TI is a usually a good source, but I have found issues with their code examples.
#define ENABLE_PINS 0xFFFE
WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer
PM5CTL0 = ENABLE_PINS;
PJSEL0 |= BIT4 | BIT5; // Set shared IO to use 32.678 kHz XTAL
// Startup clock system with max DCO setting ~8MHz
CSCTL0_H = CSKEY_H; // Unlock CS registers
CSCTL1 = DCOFSEL_3 | DCORSEL; // Set DCO to 8MHz
CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK; // CLKA = LFXT; SMCLK & MCLK = DCO
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers to 1
CSCTL4 &= ~( LFXTOFF ); // Enable LFXT
// Wait until oscillators settle down
CSCTL5 &= ~(LFXTOFFG ); // Clear LFXT fault flag
SFRIFG1 &= ~OFIFG;
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
CSCTL0_H = 0; // Lock CS registers
TA0CTL |= TASSEL__ACLK;
TA0CCR0 = 24; // Set to 1 less than the period than you desire
TA0CTL |= MC__UP; //count till TA0CCR0
P4DIR |= BIT7; //P4.7 output
P4OUT |= BIT7;
TA0R = 0; // Reset timer A
TA0CCTL0 = CCIE; // TACCR0 interrupt enabled
if((TA0CTL & TAIFG) == 1) //if flag is set
P4OUT ^= BIT7; //toggle P4.7
TA0CTL &= (~TAIFG); //clear the flag