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Consider a cmos op amp in non inverting configuration. For a small load current, we expect the output DC voltage to be the input DC voltage multiplied by closed loop gain. As the load current is increased, DC open loop gain reduces. For e.g, the open loop gain can reduce from 80dB to 40dB as the load current increases from 10mA to 30mA. 40dB of open loop gain corresponds to an error in closed loop gain of about 1%. Will the DC output voltage reduce by 1% as the load current changes from 10mA to 30mA? It doesn't seem to be the case from simulations.

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  • \$\begingroup\$ "As the load current is increased, DC open loop gain reduces." Where did you learn that? Can you give a link? \$\endgroup\$
    – Transistor
    Mar 17, 2020 at 14:16
  • \$\begingroup\$ My understanding is that as the load current is increased, eventually the output pmos/nmos will go out of saturation, causing the gain to reduce. \$\endgroup\$
    – Hrishikesh
    Mar 19, 2020 at 5:27

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Fully BIPOLAR opamps may have gain reduction as Iload increases, what with operating point variation as finite-beta reflects Iload back into HighZ nodes. This would be similar to a change in Early voltage.

Fully CMOS opamps, with the load merely changing the Vout as the FETs' triode-region alters with a true ohmic delta_Volts = Rtriode * delta_Iout, are exhibiting a voltage_divider effect which is not a genuine drop in forward voltage gain.

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  • \$\begingroup\$ Thanks for your answer! "Fully CMOS opamps, with the load merely changing the Vout as the FETs' triode-region alters with a true ohmic delta_Volts = Rtriode * delta_Iout, are exhibiting a voltage_divider effect which is not a genuine drop in forward voltage gain." Are you saying that when the open loop gain is small, the output voltage would be decided by a voltage division between Rload and the mosfet resistance in triode region? And when the gain is large, output DC voltage would be closed loop gain times the input DC voltage? Then at what gain will the 1st mechanism take over the 2nd? \$\endgroup\$
    – Hrishikesh
    Mar 19, 2020 at 5:37
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This is what I understood from simulations. Assume that the op amp consists of a differential stage as first stage and a single ended stage as the 2nd stage. As the load current increases, the gate voltage of the 2nd stage input device changes, which is the same as the 1st stage output. This results in a higher differential output in the first stage, compared to the case with 0 load current. The offset resulting from this would be the differential output divided by the gain of the 1st stage. So it is more of the 1st stage gain which decides the output voltage error.

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