# How to reduce the clock jitter for an ADC?

Of course I could buy an OCXO which has an excellent phase noise, but I cannot afford to spend 300$for an oscillator. Especially if the board could have multiple ADC... I have read some app notes that explain the usage of PLL to remove the phase noise from a clock. Ok, but then it's the VCO of the PLL that needs to be expensive as far as I understand. And the PLL chip adds phase noise also. Even with a perfect VCO, the jitter induced by the output driver of the PLL is around 100 fs. Thus it doesn't seem to be the solution. Thus my question is multiple : • How to clean up the clock from a reasonably good oscillator? I thought about using discreet filters, but the phase noise energy that creates the jitter is very close to the oscillator nominal frequency. I would have to use a band pass filter with a bandwidth of ~10khz at 130Mhz! Is it possible to do ? (bellow 200$ otherwise it would be cheaper to buy the OCXO)

• If there is no way to achieve this level of jitter of ~80fs (phase noise from 10Hz to 260MHz) by myself, where can I buy oscillators that have this level of performances with reasonable cost? The problem is that OCXO are extremely stable over time ( years ) and are usually used for that. But here I don't care, it's the phase noise that is relevant to me. Is there oscillators technologies that are very clean, but that drift over years?

• How you, amateur radio guy who have a SDR system, or engineers that design high speed ADC, solved the problem?

As you can see, I have spent a LOT of time reading app notes on the subject on the web, thus I have a deep understanding on how it works. I am a bit pessimistic about this and start to believe that there is no way to obtain a low jitter clock without getting a ~100\$+ OCXO...

First thing you need to recognize is that designing with a 16-bit ADC is not trivial. Even at 1 sample/s, you need to pay extreme attention to every aspect of the design to achieve 16-bit precision, or even more difficultly, 16-bit accuracy. At 130 MSa/s, everything is even more difficult.

The parts you need to do this kind of design simply won't be inexpensive. First, because of the extreme precision and careful testing needed to achieve the required performance. Second, because this kind of thing isn't done in mass-market products, so the parts aren't built in the kind of extremely high volumes that can bring the price down for everyone.

As Dave says in another answer, be sure you really need 16 bits before you go down this road. But maybe you really need 12-bit precision, and you know that if you use even a 14-bit ADC you're going to have a hard time achieving that, so you're designing with 16-bit ADC and optimize everything else as much as you can.

Another key is likely to be understanding exactly what specs you need to make your system work, and don't over-specify your clock jitter. In an SDR application, you're going to be doing math on the samples to extract specific frequency bands, etc, which will have an averaging effect over many cycles. So you might not care too much that absolutely every sample is timed perfectly, only that over your calculation interval, there isn't too much deviation from ideal timing. How much is too much, of course, depends on what kind of math you're doing and how small a signal you need to extract from how much noise.

CTS Valpey, for example, has XO's with rms jitter specs as low as 200 fs. But this spec is defined when the phase noise is integrated over a specific frequency band, 12 kHz to 20 MHz (relative to the carrier). If the total cycle-to-cycle jitter is considered, the spec jumps to 3-6 ps, depending on the center frequency.

OCXO are extremely stable over time ( years ) and are usually used for that.

The "ovenized" part of that product mainly reduces the drift due to temperature change in the surrounding environment, which can be significant over time scales of minutes or seconds, not just years. It will also reduce wear on the part due to thermal cycling and improve the stability on a time scale of years.

For the < 100 fs jitter range you're looking for, you might actually need an OCXO to prevent small temperature changes affecting the performance during the time it takes to measure the jitter accurately enough to know you've achieved your spec.

The answer was to use a PLL chip. It adds wide-band noise, but this could be filtered using a pass-band SAW filter of 12kHz band at its output.

Basically the PLL keeps the close-in noise of its reference clock and rejects its wide-band noise. The opposite applies for the VCO of the PLL.

Thus the game was to find an oscillator with excellent close-in noise, disregarding its wide-band noise floor. And also find a VCO that has a very low noise at ~10kHz from the nominal frequency, disregarding its response at closer frequencies.

The noise at the output of the PLL will be a combination of the close-in noise of the reference frequency, the noise of the VCO between 1kHz to 12kHz, and the wide-band noise floor of the PLL chip output driver.

The SAW filter will remove the noise above 12kHz and the final response has a very good phase noise that, when converted into jitter (10Hz to 230MHz), creates a jitter of ~90fs ! Which is good for the application.