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I am running a 3.3V 20MHz clock signal for LED drivers over 10 PCBs that are connected to each other over short cables. Overall, the clock signal must travel 1m.

Is this even possible with a 20MHz clock signal without using a buffer on each board? Will I run into EMI issues even if I route the clock signal carefully (e.g. applied best-practice PCB design rules for routing clocks)?

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    \$\begingroup\$ What IC part number are you using to drive the clock? Is the application really so cost sensitive you can't afford a $0.10 buffer on each board? \$\endgroup\$
    – The Photon
    Mar 17, 2020 at 18:28
  • \$\begingroup\$ I am using the TLC5948A. A buffer would be an option, but the space on the board is limited. Could you suggest a part with only 1 clock output? \$\endgroup\$ Mar 17, 2020 at 18:45
  • \$\begingroup\$ 74lvc1g125 is a single buffer available in SC-70 package. \$\endgroup\$
    – The Photon
    Mar 17, 2020 at 18:48
  • \$\begingroup\$ Thank you. Is there a Pullup resistor needed for the clock output? \$\endgroup\$ Mar 17, 2020 at 19:01
  • \$\begingroup\$ I am just realizing that buffering all signals, not only clock, might be a good idea. \$\endgroup\$ Mar 17, 2020 at 19:21

2 Answers 2

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Is this even possible with a 20MHz clock signal without using a buffer on each board?

It all depends on the drive-strength of the clock source, how many milli-Amperes can it source? You can approximate the trace resistance using:

  • trace width and copper thickness on the PCBs
  • wire gauge on cable

and figure out the DC loss at the end of the chain. That should give you a good idea of what voltage level (from the original 3.3V) you'll get on the input of the last LED driver.

If the voltage swing is not sufficient, you may want to add a buffer mid-trace. Do you need all LED boards to be identical? In this case, you could implement the buffer circuit and add a 0-Ohm bypass resistor. For 9 of your PCBs, the 0-Ohm would be loaded and the buffer circuit unloaded. For the last, the 0-Ohm resistor would be unloaded and the buffer circuit loaded.

Will I run into EMI issues even if I route the clock signal carefully (e.g. applied best-practice PCB design rules for routing clocks)?

Generally, a swinging 3.3V signal at this frequency going over such a length is an EMI concern. I don't believe your setup will act as an antenna for the main frequency (wavelength is 15 meters for 20MHz signal) but it could well be for harmonics of the signal.

There are a few things you could implement to anticipate EMI mitigation:

  • software control over the clock source drive-strength: you could try to find the lowest drive-strength setting still meeting the waveform requirements for all LED driver's inputs. The lower the current, the lower the EMI. The slower the signal edges, the lower the EMI
  • hardware control over the clock source drive-strength: if you don't have software control, you may want to add an RC circuit next to the clock source pin, load it with a 0-Ohm resistor and leave the capacitor footprint open. You can use this circuit to control the current and shape of the source waveform and perform the same EMI improvement as described above. The capacitor can help with rounding corners of the edges of the waveform, helping to reduce the harmonics of the signals
  • add termination resistor near each LED drive input: the LED driver input is high-impedance so to avoid reflection and any other side-effect, you could size the resistor value to match the line impedance
  • if you have the option of sandwiching the clock signal between 2 ground planes and using shielded or semi-shielded cable, this could help with blocking the magnetic field therefore potentially help lower EMI.

EDIT: ESP32 module drive-strength information

On page 44 of the ESP32's datasheet, you'll find this note: enter image description here

Your clock trace has a certain resistance value (but very tiny) and is capacitively coupled to your ground plane. The ESP32 pin, the connector contacts, LED driver inputs, etc. all have parasitic capacitances. Now, if you simplify, imagine the clock trace being a simple RC circuit. The more current you can push into it, the faster the capacitor will charge. In other words, the more current you push into your clock trace, the faster it will rise to 3.3V. Same for discharge, the faster you can sink current, the faster your clock signal will fall/discharge to ground.

What that table tells you is that you can control the current you can push (source) and sink for each I/O pin. I did not verify if the PWM output you are using for your clock signal does have this feature, however, I'm sure you can find this out yourself :)

Now let's say the drive-strength control is missing from your PWM pin, what I was suggesting you can do is add a parallel capacitor, as increasing the capacitance of your trace will result in slower charge/discharge and therefore slower edges (eg. improved EMI).

Again, be sure to meet the timing requirements for all the LED driver inputs when lowering drive-strength or adding an external capacitor, if the edges are too slow the drivers won't work as expected.

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  • \$\begingroup\$ How can the clock source adjust the drive current? Doesn't the LED drive have a high impedance input and this it what sets the current? \$\endgroup\$ Mar 23, 2020 at 22:57
  • \$\begingroup\$ What device is used to generate the clock source? Some CMOS circuits have drive strength control, which is a measurement of how much current can be driven to the load. In this case, the LED driver is a high-impedance load and does not set the current. \$\endgroup\$
    – eeintech
    Mar 24, 2020 at 13:33
  • \$\begingroup\$ I am using ESP32's LEDC output for generating the clock. I still don't understand how you control the strength. If LED driver input is high impedance (say in Meg Ohm range) and voltage is given with 3.3V, then this determines the current, right? \$\endgroup\$ Mar 24, 2020 at 19:04
  • \$\begingroup\$ @F.Heisenberg I added an edit to my answer in an attempt to answer the question in your previous comment. \$\endgroup\$
    – eeintech
    Mar 24, 2020 at 21:15
  • \$\begingroup\$ this makes it very clear now, thank you. \$\endgroup\$ Mar 25, 2020 at 22:22
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I don't think you have any chance at all of getting this to work. The distance (1 m), multiple loads (which probably mean multiple unterminated stubs), and the fact that what you have is a single ended (as opposed) to differential interface are all working against you. This is a signal integrity (SI) nightmare.

If you think otherwise, I would like to see a simulation and SI analysis that shows this working.

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  • \$\begingroup\$ I understand so far that I would need a couple of buffers along the way to ensure signal integrity. I am quite new to PCB layout - is it even possible to do simulations with cables inbetween PCBs? \$\endgroup\$ Mar 23, 2020 at 22:55
  • \$\begingroup\$ Yes. Hyperlynx (part of the Mentor Graphics tool suite) can do that. You can mix and match interface types (signal over ground, wires, cables, etc) to your hearts content. \$\endgroup\$
    – SteveSh
    Mar 24, 2020 at 0:06

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