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I'm designing a solid state battery disconnect switch and I want to improve the mosfets' turn-on immunity (high dV/dt on Vds) without impacting the turn-off time. I don't really care about the turn-on time, it can be 100x slower than turn-off time, no problem.

I came up with this solution:

enter image description here

C1 obviously improves the immunity and D1 should leave the turn-off time the same. Did I miss something? is there a better way to do this?

NB: mosfet's datasheet is available here and the driver's datasheet is here. I'll use a +/- 12 V symmetric supply and the driver will drive 10 mosfets in parallel.

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  • \$\begingroup\$ How does D1 prevent C1 from slowing turn off? \$\endgroup\$ – evildemonic Mar 17 at 22:27
  • \$\begingroup\$ What exactly do you mean by mosfet's dynamic turn-on immunity? Do you mean unwanted switchg on of the MOSFET via noise? \$\endgroup\$ – vtolentino Mar 17 at 22:34
  • \$\begingroup\$ @evildemonic It avoids C1 discharging into the driver's output when it goes low. \$\endgroup\$ – Biduleohm Mar 17 at 22:35
  • \$\begingroup\$ @vtolentino I mean unwanted turn-on if Vds rises quickly. \$\endgroup\$ – Biduleohm Mar 17 at 22:37
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    \$\begingroup\$ infineon.com/dgdl/… page 11 and 12 \$\endgroup\$ – Biduleohm Mar 17 at 22:45
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I simulated your circuit using a similar FET with a transient suppressor added, switching a 'short circuit' drawing 1000 amps from a 50 V battery with 10 nH of wiring inductance. It 'worked' in that it had no effect on the switch-off time or power dissipated during the transition. However in this scenario the transition is slowed down by Miller effect, so (assuming adequate transient suppression) you should not have to worry about Dv/Dt causing the MOSFET to turn on again.

So when might Dv/Dt be a problem? One possibility could be if the battery is plugged in while the FET driver is not powered. In this case there could be a fast rising Drain voltage with only weak resistance pulling the Gate down. But would this cause the FET to turn on? Looking at the MOSFET's capacitance graph we see that Gate-Drain capacitance is ~800 pF at 50 V, while Gate-Source capacitance is ~12 nF. That corresponds to a division ratio of 16:1, so 50 V on the Drain could produce ~3.1V on the Gate. As the threshold voltage is between 2 and 4 V the FET might partially turn on for a few microseconds.

By adding extra capacitance to the Gate your circuit increases the capacitive division ratio which makes the power-on transient Gate voltage lower, (hopefully) ensuring that the FET stays turned off when an external voltage is applied.

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  • \$\begingroup\$ I was somewhat concerned about the inductive spike at turn-off but after a few calculations I deemed it not a problem, not enough inductance. Connecting the battery to something (while the mosfet is or isn't powered, even if when it is it should not be a problem as the gate will be at a negative potential) is effectively my main concern. I'll have a Vds of 64 V maximum and I use the worst case which is Vgsth = 1.2 V @ 120 °C and Crss = 1.7 nF @ a low Vds. Also, I wonder what might be adequate transient suppression because I already thought about it and I'm not sure a TVS diode will be enough. \$\endgroup\$ – Biduleohm Mar 18 at 13:00
  • \$\begingroup\$ If the Gate is pulled negative then it shouldn't be a problem because capacitance will be discharged quickly. If switching off very high current you need very high current transient suppression - I used 6 5W Zeners in parallel in my simulation and it was barely enough. A good TVS should do it. \$\endgroup\$ – Bruce Abbott Mar 18 at 20:21
  • \$\begingroup\$ My worry is more if the control circuitry isn't powered. Ok, I guess this one isn't gonna be good enough (I already use it somewhere elsein the project), maybe this one then? \$\endgroup\$ – Biduleohm Mar 18 at 20:36
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Your MOSFET driver 1EDI has excellent description !

"The 1EDI EiceDRIVER™ Compact is a general purpose MOSFET gate driver. .... The separated rail-to-rail driver outputs simplify gate resistor selection, save an external high current bypass diode and enhance dV/dt control."

So You can control On and Off time simply by selecting two resistors: Ron from Out+(ON) to Q1gate andenter image description here Roff from Out-(OFF) to Q1gate;

There is no need of any other components!

time on = Ron.Ciss; time of = Roff*Ciss;

{FDBL86361-F085 Ciss Input Capacitance VDS = 40 V, VGS = 0 V, f = 1 MHz − 12800 − pF}

Aprox. calculations for single MOSFET: Ron=100R; Ciss=13nF=12e-9F; Ton=1.3e-6s = 1.3uS
Roff=10R; Ciss=13nF=12e-9F; Toff=1.3e-7s = 130ns

If you will drive 10 mosfets in parallel then Ciss will increase 10 times.

About driver supply: It is better to use bipolar to "prevent a dynamic turn on of the MOSFET". P.S. If you want to decrease dV/dt simply add an inductance to the load in series. (with all the consequences)

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  • \$\begingroup\$ That's not what the question is about and I already have different resistors for the turn-on and turn-off outputs of the driver. The driver can even be left out of the equation here. Given a high enough dV/dt of Vds the mosfet will turn-on, that's what want to prevent (even when the driver isn't powered). \$\endgroup\$ – Biduleohm Mar 27 at 21:33
  • \$\begingroup\$ What is the type of the load and why are these precautions? \$\endgroup\$ – Peter MP Mar 28 at 1:19
  • \$\begingroup\$ Typical loads would be inverters, lights, motors. I'm not trying to protect against loads but against the act of connecting the battery to something or even if there's a short circuit. You can consider the following: battery negative is connected to the source, the driver isn't powered (so you can ignore it), the mosfet should not turn on if you connect the battery positive to the drain instantly. \$\endgroup\$ – Biduleohm Mar 28 at 2:08
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Besides your suggestion, there is something else you can do in order to reduce the unwanted gate voltage rise due to the parasitic leakage current.

Consider the following circuit: The mosfet is permanently grounded through the resistor R1 and a square wave with a slew rate of 100n is applied to its drain.

How it works: the leakage current is mostly a function of the parasitic capacitance and the slew rate dV/dt of the drain voltage. Thus, once the drain voltage starts to increase, part of it is coupled through the capacitor C2 and used to turn on the BJts. Due to their high speed, a few bipolars are connected in a cascade fashion in order to increase even more their gain. For a short moment, the gate of the mosfet is shorted and the parasitic capacitance is discharged.

In the waveform you see the effect of not using the circuit (C2 ~ 1p) and with a coupling capacitor (10n). Using this approach the gate voltage dropped by half. I must say that I never saw something like that in any application. The slew rate used in the simulation is extremely high (fast), and probably does not represent a real load.

P.S.: I did not consider any side effect of this proposal.

Circuit

Waveform

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  • \$\begingroup\$ That's an interesting solution. But I can't see how Q2 and Q3 can amplify anything as they're not connected to anything else than the signal they should amplify; but I see the idea. I'm not a huge fan of connecting the power side to the gate, there's too many variables (like in my case Vds can be negative for example) to take into account and I'm afraid to forget something and have big problems. \$\endgroup\$ – Biduleohm Mar 18 at 0:56
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I used the solution I gave in the question with:

C1 = 100 nF (min 90.7 nF calculated with Crss = 1.7 nF, Vds = 64 V and Vgsth = 1.2 V)
R1 = 47 k (value not critical, BoM reuse)
D1 = STPS1L30

Also be warned the inductive voltage spike at turn-off is actually a significant problem contrary to what I thought, you must do something about it if your application is similar to mine. NB: TVS/zener diodes aren't good enough if your working voltage is 64 V and the mosfets have a Vdss of only 80 V.

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Why not simply increase the switch-on resistance by adding R3?

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ That's not what the question is about and I already have different resistors for the turn-on and turn-off outputs of the driver. The driver can even be left out of the equation here. Given a high enough dV/dt of Vds the mosfet will turn-on, that's what want to prevent (even when the driver isn't powered). \$\endgroup\$ – Biduleohm Mar 27 at 21:29
  • \$\begingroup\$ @Biduleohm I misunderstood your question then. For protection against \$dV_{DS}/dt\$ you have to add a snubber between D and S. \$\endgroup\$ – skvery Mar 28 at 5:50
  • \$\begingroup\$ I can't rely on a snubber because the power source is a battery capable of delivering kA so a snubber would be either too big and expensive or uneffective. \$\endgroup\$ – Biduleohm Mar 28 at 15:24

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