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So I'm totally new to this and sorry if this is a really basic question which answer is in the error message. I get the error: [DRC NSTD-1] Unspecified I/O Standard: 5 out of 25 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards.

I know which pins are at fault but I cannot assign them values directly: assignment to a non-net is not permitted.

I've been trying to fix this for a few hours and I'm quite at a loss. I don't want to create a tcl file as it says this may damage the board and this board is quite expensive.

Also this happens when combining two modules. The modules by themselves with the same code run fine. Thanks in advance!

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  • \$\begingroup\$ Oh, I think I have it. Is it possible that I'm not allowed to rename the "variables" in another module after having declared constraints? \$\endgroup\$ – Oli Mar 18 at 17:20
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Thats a wrong conclusion you are leading to , whenever you have designed the verilog/vhdl module in the constraints file you need to provide the following information,

  • Physical constraints -- Pin location constraints, IO Standard of IO pin(you can see the VCCO,VCC_AUX values in case of xilinx fpga similarly you can see for other FPGAs too),Slew constraints, Equalization of IO for high speed transceivers
  • Clock constraints (create_clk constraints)
  • False paths or MCP paths or Max delay paths (CDC)
  • any other constraints

    module top (input nota, input b, output c) ;
    
    example u_example (
      .a (~nota )
     ,.b (b     )
     ,.c (c     )
    );
    
    endmodule 
    

    module example (input a, input b, output c); //...definition of module ...// endmodule

Constriants

  • set_property PACKAGE_PIN AM17 [get_ports "nota"] ;
  • set_property PACKAGE_PIN AM16 [get_ports "b"] ;
  • set_property PACKAGE_PIN AM15 [get_ports "c"] ;
  • set_property IOSTANDARD LVCMOS12 [get_ports "nota"] ;
  • set_property IOSTANDARD LVCMOS12 [get_ports "b"] ;
  • set_property IOSTANDARD LVCMOS12 [get_ports "c"] ;
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  • \$\begingroup\$ Hi Rama, thank you. So I could have different variable names? \$\endgroup\$ – Oli Mar 19 at 10:19
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    \$\begingroup\$ yep u can have different variable names , u need to connect through the named port connections, for the top module ports it is showing as 5 ports IO standard u didn't defined, u can define them thats it, it is nothing to do with the variable names .. or else u can see if ur code got optimized through schematic viewer \$\endgroup\$ – RAMA KRISHNA MEDA Mar 19 at 10:32
  • \$\begingroup\$ Thank you so much! I'll try to optimize now and see if I can come up with something prettier \$\endgroup\$ – Oli Mar 19 at 10:51
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    \$\begingroup\$ that shouldn't be the case , if u dont mind please post the code snippet and constraints of the top module in ur design \$\endgroup\$ – RAMA KRISHNA MEDA Mar 26 at 12:04
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    \$\begingroup\$ Glad to hear!! U are out of errors. Feel free to ask new questions too \$\endgroup\$ – RAMA KRISHNA MEDA Mar 26 at 15:12
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I solved it, I actually answered this with my question above.

I doubt that there will be another noobie like me having such a basic question but here it goes.

Once you declare a constraint name and implement it in a module. It seems that this constraint can not be renamed and passed from another module. It has to have the same name.

Example some pin named a. module example (input a, input b, output c) something endmodule module top (input nota, input b, output c) input nota isn't going to work you need input a. At least I needed it.

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    \$\begingroup\$ Top marks for returning to write up the answer properly, many don't bother once their problem's gone. A very warm welcome to the site. \$\endgroup\$ – TonyM Mar 18 at 17:39

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