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Please have a look at my below circuits.

The first one is an MOSFET. N-MOS.

Gate is fed with a function generator input of 5V peak to peak. 1kHz frequency. 1ms period. 90% duty cycle. Drain is provided with 10V and the source is connected to a load resistor.

enter image description here

If I probe at the gate and the source, I get the below waveform :

enter image description here

Please consider only the yellow and blue trace in the above waveform. Yellow is probed at the gate. Blue is probed at the source of the MOSFET.

If I connect the MOSFET to the circuit shown above, i.e., my second circuit, the same FG input is provided to the GATE of the MOSFET.

Now, I probe at the point A and the Gate of the MOSFET. Below is the waveform :

enter image description here

Yellow is the GATE of the MOSFET. While blue is probed at Node A.

My questions are :

  1. In the second waveform and the second circuit, shouldn't the voltage at node A, follow the voltage at the GATE of the MOSFET? The node A voltage should also go to 0V while the Gate voltage goes to 0V. Why am I not getting that 0V waveform at the Node A?
  2. What effect does the resistor connected to the source of the MOSFET and the purpose of the C1 50nF capacitor in this circuit.
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  • \$\begingroup\$ Understand (2) - specifically, read about what a capacitor does, and that will explain (1). \$\endgroup\$ – Brian Drummond Mar 18 at 17:18
  • \$\begingroup\$ When the FET is on, charge flows into the caps. When the FET is off, no new charge is supplied. Unless you have a downstream short you don't mention, think about what node A voltage would do as the cap's stored charge flows to ground through the resistors over time. \$\endgroup\$ – schadjo Mar 18 at 17:22
  • \$\begingroup\$ I tried to understand but not getting totally clarity on this topic. I know I am missing to fit the very basic function of capacitor and the MOSFET and the downstream load. Could someone please help me with an answer \$\endgroup\$ – Newbie Mar 18 at 17:26
  • \$\begingroup\$ @Newbie As the name would suggest, a capacitor holds charge. When you turn on the FET, the cap fills up quickly because there is no significant resistance preventing current from flowing into the cap, from the supply through the FET. But when you turn off the FET, the current (charge stored in the cap) can flow from the cap to ground through the resistor. I recommend simulating the circuit and figuring out where all the currents flow during on and off states. I think this will give you insight into what you're seeing. \$\endgroup\$ – schadjo Mar 18 at 18:22
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  1. It does. But the capacitors hold some charge for a while before losing it slowly. Without capacitor voltage falls immediately. This is normal.

  2. This resistor limits the current being sunk to ground. Without it you would create a short circuit situation.

IMO this circuit is build upside down. The resistor should be on the drain side (to be a pull up resistor. Value between 10K to 50K at 10V) with all the capacitors and stuffs, and the source connected to GND directly. While the current setup works in practice, it's not intended to work like that.

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  • \$\begingroup\$ Thank you for the answer. But Could you please elaborate a little more on your first point. Like, for how long can the capacitor hold the charge/voltage before going down? Can I use I=C(dv/dt) , to figure out the dip in voltage during that time? Please elaborate a little more. And why should the resistor be connected to the drain and not the source. Effectively, the resistor plays the same role in both the location. \$\endgroup\$ – Newbie Mar 19 at 2:48
  • \$\begingroup\$ @Newbie The resistor must be connected to the drain because the N-Mosfet is buoild to sink current to ground. If there are effect beyond the source pin it's only to the extent some current went to ground, (more technical details on websites dedicated to mosfets). About time for capacitor chargng and dechargoing, look here: electronics-tutorials.ws/rc/rc_1.html \$\endgroup\$ – Fredled Mar 20 at 0:59

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