I have an output stage. The circuit diagram is as shown:

enter image description here

In DC condition, the node X has a DC voltage of Vdd/2. The node Z has a voltage of about 1.26 volts. Vdd = 3.3 volts. Transistors M7 and M5 have same W/L and so is the case with M6 and M8. The current through both the branches is the same around 50 uA. Both X and Z nodes are unloaded, i.e open. Now here are my questions:

  1. Why does node X settle to vdd/2?

  2. Why node Z does not settle to vdd/2?

Here is my attempt at the solutions:

  1. Considering the output branch, Id will be the same through M7 and M8, if both are in saturation then the standard equation \$ I_d = K(Vgs-Vth)^2 \times (1+\lambda Vds) \$. Since Id is the same, Vgs for both the transistors is 1 volt, \$\lambda \$ is negligible because the channel length of both the transistors is long. What remains is the factor K and Vth. Unfortunately i cannot find the technology values hence I would like to know whether this analysis is correct so that i can blindly blame K and Vth :). If that is true then somehow all the values come together in the branch with node X to get X at vdd/2.
  2. Second line of thought are the caps Cds of M7 and M8. they are in series and using the capacitor voltage divider rule, the voltage at node Z and similarly for ode X can be estimated. I checked the capacitance but the voltage at node Z and X do not check out with this theory.

Any help will be appreciated.

Edit: Also if i consider the first line of thought, that since Id is the same in the output branch, therefore M7 and M8 will force the voltage at node Z such that Vds for both transistors are enough for the current of 50 uA to flow. If thats the case, then what needs to be changed (w/l, bias current) to get node Z to vdd/2

  • \$\begingroup\$ Is there a load connected? If so, what impedance? \$\endgroup\$ – user_1818839 Mar 18 '20 at 19:06
  • \$\begingroup\$ @BrianDrummond No there is no load connected, like i mentioned in the post, both Xand Z are open \$\endgroup\$ – RAN Mar 18 '20 at 19:27

No, it’s not a classic AB stage. The front end is more like AB because it is a push pull source follower and has a gain of unity AND will exhibit close-to-mid-rail performance.

The output stage on the other hand has a massive voltage gain that will exploit any subtle differences in the MOSFETs. It’s not an AB stage at all.

  • \$\begingroup\$ Yup correction made \$\endgroup\$ – RAN Mar 18 '20 at 20:43
  • \$\begingroup\$ Ok the gain is really high, because its an inverter stage, but still can you please explain why the voltages? \$\endgroup\$ – RAN Mar 21 '20 at 12:46
  • \$\begingroup\$ Differences between p and n channel MOSFETs. \$\endgroup\$ – Andy aka Mar 21 '20 at 14:36
  • \$\begingroup\$ OK, but i am trying to figure out what difference causes it, is it the small signal resistance, or the Cds of both the mosfets, given equal Vgs \$\endgroup\$ – RAN Mar 22 '20 at 16:32
  • \$\begingroup\$ Also while talking about DC voltages, do AC parameters really matter? \$\endgroup\$ – RAN Mar 22 '20 at 19:47

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