I have an output stage. The circuit diagram is as shown:
In DC condition, the node X has a DC voltage of Vdd/2. The node Z has a voltage of about 1.26 volts. Vdd = 3.3 volts. Transistors M7 and M5 have same W/L and so is the case with M6 and M8. The current through both the branches is the same around 50 uA. Both X and Z nodes are unloaded, i.e open. Now here are my questions:
Why does node X settle to vdd/2?
Why node Z does not settle to vdd/2?
Here is my attempt at the solutions:
- Considering the output branch, Id will be the same through M7 and M8, if both are in saturation then the standard equation \$ I_d = K(Vgs-Vth)^2 \times (1+\lambda Vds) \$. Since Id is the same, Vgs for both the transistors is 1 volt, \$\lambda \$ is negligible because the channel length of both the transistors is long. What remains is the factor K and Vth. Unfortunately i cannot find the technology values hence I would like to know whether this analysis is correct so that i can blindly blame K and Vth :). If that is true then somehow all the values come together in the branch with node X to get X at vdd/2.
- Second line of thought are the caps Cds of M7 and M8. they are in series and using the capacitor voltage divider rule, the voltage at node Z and similarly for ode X can be estimated. I checked the capacitance but the voltage at node Z and X do not check out with this theory.
Any help will be appreciated.
Edit: Also if i consider the first line of thought, that since Id is the same in the output branch, therefore M7 and M8 will force the voltage at node Z such that Vds for both transistors are enough for the current of 50 uA to flow. If thats the case, then what needs to be changed (w/l, bias current) to get node Z to vdd/2