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schematic

simulate this circuit – Schematic created using CircuitLab

Given this circuit of a common source amplifier with a resistive load, I know that as long as the signal source $$A\sin(\omega t)$$ is small enough and the operating point lies in the saturation region we can do the regular small signal analysis to find Vout. There will be a negative incremental gain. Similarly, based on what I understand , if the operating point were in triode region the output voltage will still show some negative incremental gain but much lower than the gain in the saturation region. Please correct me if I am wrong.

I would like to know what happens if the operating point is in the saturation region, but the signal is large enough to drive $$v_{GS}$$ to cutoff and triode regions(each on either half cycles). What will the trans conductance look like then?

Here is what I thought about it:if $$v_{GS}$$ were to be driven to the cutoff region, $$V_{GS}+A\sin(\omega t)$$ should become very low. So this should obviously mean this occurs below some point in the negative half cycle of $$A\sin(\omega t)$$. In the cutoff region, no current flows through the MOSFET, so no current must flow through R3. Therefore, $$V_{out} = VDD$$. Similarly, triode region must occur above some point int the positive half cycle. In the triode region gain will be lower. So I arrived at the following graph(attached), which is obviously wrong because it has discontinuities in it, but I don't understand why it is wrong. For the trans conductance part, I am totally confused. Are we supposed to consider the signal source also to plot it because it is not "small enough" anymore or is it a constant straight line at $$K_n\frac{R_1}{R_1+R_2}V_{DD}$$. enter image description here

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This gives class_C operation, the best efficient RF mode. just follow the FET with PI matching.

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  • \$\begingroup\$ I am sorry,but I am not sure I understand your answer. I have just begun studying analog electronics. \$\endgroup\$ – Gayatri Mar 19 at 4:14

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