The main link for the logic for the individual segments is that they must share the same inputs. Optionally, they can share computation of a given expression: for example, inverted values of all the inputs occur more than once, so you can share the output of the invertors (
A./B occurs twice and could be done with a single AND.
If you're implementing in gates, you can pretty much directly convert to logic as shown in the circuit below. You may well find that some terms can be optimised because they are shared between segments: for example, I've shared
/B etc, but you can find shared terms after the AND gates. (NB: following is for common cathode seven-segment display, common anode would be similar but with some logic reversal, as you generate
/outa etc, not
outa.) I don't know what gates you consider acceptable, I'm using maximum of 3-input ANDs and ORs just because the schematic capture of stackexchange has those. You might well want 7- and 6-input OR gates, depending on what you're implementing in.
If you actually build it, you can really see the value of programmable logic arrays, printed circuit boards, and MSI. Or of course microcontrollers, where the whole thing is just something like
portb = segmentmap[x & 0xf];.
simulate this circuit – Schematic created using CircuitLab
You might be interested that the datasheets for 74LS47 seven-segment decoders give the following (though note they don't give hex output for 10-15):
From Texas Instruments 7447 Datasheet
Second Half of Question
Since you updated with your separate logic blocks, you need to join all the a, b, c, d inputs to each block together, so that each block calculates the its segment value for the same inputs.
I'm not sure what simulator package you're using, but you'll want something like the following, which should display a 9 if the logic is correct.