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I have just started learning Verilog, so I tried writing a simple 4-bit binary counter. However, when I run the behavioural simulation, the output stays undetermined. I will really appreciate if someone can tell me where I am going wrong.

module counter(input clk, input rst, output reg [3:0] count);

always@ (posedge clk)
begin

    if(rst)
        count <= 4'b0;
    else
        count <= count + 1'b1;
end

endmodule

Here is a screenshot of the behavioural simulation

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    \$\begingroup\$ Toggle your reset line to initialize the count reg. \$\endgroup\$ – schadjo Mar 19 '20 at 19:46
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    \$\begingroup\$ u could have posted full picture of simulation.anyways as @schadjo mentioned this due to the missing of reset pulse. or else u could do module counter(input clk, input rst, output reg [3:0] count = 0); \$\endgroup\$ – RAMA KRISHNA MEDA Mar 20 '20 at 8:57
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Your count starts at X (actually it starts 4'bxxxx.).

Now if you add 1'b1 to 4'bxxxx you still have 4'bxxxx. Sort of like a dead-lock

The only way to break this deadlock in your code is to apply a reset whilst the clock is running. That forces the counter to zero and after removing the reset you can use it to count.

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