I need to run a 3.2 Gb/s interface over 50m. My client is keen on Cat6e. The lower the price, the better. These are my findings so far:
I'm looking at using a Spartan 6 GTP Tranceiver with copper (Cat6/6a). I've spent most of the past few days digging through Xilinx's documentation on high speed tranceivers (mostly http://www.xilinx.com/publications/archives/books/serialio.pdf), however I'm still a bit unsure about this. The following is what I've found:
- The above document mentions that copper is OK for less than 6 Gb/s (GTP max is 3.2 Gb/s, so cool) and for distances less than 20m (I'm looking at 50m or so).
- The cat6a specifications are for 100m and 10Gb ethernet (so that's fine?)
So what I'd like to do is maybe use Xilinx 10Gb Ethernet core in the FPGA with the GTP transceiver. (This core: http://www.xilinx.com/support/documentation/ip_documentation/ten_gig_eth_mac_ds201.pdf)
That document mentions that Spartan LXT is compatible with the 10Gb ethernet MAC, however, it doesn't say anything about copper, all the examples are fiber, and I'm assuming that the 10 Gb Ethernet core has a maximum speed of 10 Gb/s, but will work with lower speeds?
Is is possible to use other interfaces (AURORA, XAUI) over Cat6e as long as the specs meet the Cat6e requirements, (and considering that I'm looking at a 3.2 Gb/s interface)? Or do I need to use specific connectors/cables for Aurora/XAUI? (1 channel).
How "easy" is a board design/layout for a 3.2 Gb/s tranciever? The xilinx high-speed documentation mentions that special equipment (scopes, etc) is necessary for debugging high-speed interfaces. Since the clock period is 3x bigger than 10 Gb/s, i assume that the tight timing requirements are not as stringent?
I've used Aurora and XAUI before, but always the FPGA HDL design side, never the board design, and we always used high-speed connectors. This is my first high-speed serial board design. A second opinion would be hugely appreciated!