Understanding "stereotyped" noise on MISO line

Question

Just getting started with EE, so bear with me. I've got a bare-metal STM32G474RE communicating over SPI (~5MHz) with an LSM9DS1. I've got a probe hooked up and capturing the communication and it seems to be working well. I send 0x8F and get back 0x68 from the WHO_AM_I register:

CS/CLK/MOSI/MISO, respectively. What I'm trying to understand is the "stereotyped" noise in the signal. I understand that all signals will have some kind of a noise floor, but the MISO line is both noticeably noisier than the other lines (not clear to me why?), and the noise pattern appears to follow a consistent pattern frame-to-frame i.e. I can trigger a new recording and the signal looks almost identical.

Circled - I assume this dip that coincides with the first falling clock edge is due to the MOSI line dropping and affecting the VDD line (?).

Rect - The MISO line is super noisy compare to the MOSI. But it's not white-noise noisy; rather the ringing on the line is nearly identical each time I capture a new trigger. What might cause large-but-very-consistent noise like this?

Arrow - Not really noise-related, but I assume this gradual voltage rise back up to VDD is due to neither slave nor master driving the MISO line and there being an internal pull-up resistor + cap somewhere. Why would this happen only after CS goes high? Is it this "refactory period" what limits the SPI speed?

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Edit: more detail

The micro is on the NUCLEO-G474RE board (pdf), and the LSM9DS1 is on the breakout board from Adafruit (link). SPI port is SPI2, with pins PB 12/13/14/15 for CS/CLK/MISO/MOSI, respectively. Connected with ~4" wires terminated with 1-pin female Dupont. Let me know if you need any more details!

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Edit: Swapped probe

Swapped probes 3 and 4 on the PCB side. Noise does not follow the probe; it only appears on the MISO line.

Answer 1

Measuring with a scope is an art. It is not so much if your probes are grounded but more where they are grounded.

Noise also greatly depends on PCB layout and the drive strength. Think if it like two person side by side: You hear the one better over the other if he shouts louder.

Back to your signals:

Circle : That coincides with the first data bit. Can it be that the first data bit tells the slave to read or write? If so this is is where the MISO line goes from floating to being driven. This type of behaviour is often seen with interfaces which offer a single bi-directional data line for input and output.

Rect: Yes your signal is noisy but as said, that is often caused by a bad probe ground.I would also check if you have correct decoupling of all the chips.

Arrow: The moment the chip select goes away your MISO output goes tri-state. Indeed what you see is the floating net being pulled-up somewhere. As there is no chip-select it does not matter where that line floats to. It could also go low or go random.

"stereo-typed":Getting to the core of your question: That you see the same "stereo-typed" pattern is easily explained by the fact that noise in a digital PCB is not random but caused by the switching of the circuits. The CPU is running the same program section each time and thus you get the same noise pattern each time.
You might see a difference if the driver is handled by an interrupt in which case the noise pattern depends on where the SPI interrupt occurred.
Your noise can also be caused by the SPI slave device in which case the noise pattern is more likely to be always the same.