Just getting started with EE, so bear with me. I've got a bare-metal STM32G474RE communicating over SPI (~5MHz) with an LSM9DS1. I've got a probe hooked up and capturing the communication and it seems to be working well. I send 0x8F and get back 0x68 from the WHO_AM_I register:
CS/CLK/MOSI/MISO, respectively. What I'm trying to understand is the "stereotyped" noise in the signal. I understand that all signals will have some kind of a noise floor, but the MISO line is both noticeably noisier than the other lines (not clear to me why?), and the noise pattern appears to follow a consistent pattern frame-to-frame i.e. I can trigger a new recording and the signal looks almost identical.
Circled - I assume this dip that coincides with the first falling clock edge is due to the MOSI line dropping and affecting the VDD line (?).
Rect - The MISO line is super noisy compare to the MOSI. But it's not white-noise noisy; rather the ringing on the line is nearly identical each time I capture a new trigger. What might cause large-but-very-consistent noise like this?
Arrow - Not really noise-related, but I assume this gradual voltage rise back up to VDD is due to neither slave nor master driving the MISO line and there being an internal pull-up resistor + cap somewhere. Why would this happen only after CS goes high? Is it this "refactory period" what limits the SPI speed?
Edit: more detail
The micro is on the NUCLEO-G474RE board (pdf), and the LSM9DS1 is on the breakout board from Adafruit (link). SPI port is SPI2, with pins PB 12/13/14/15 for CS/CLK/MISO/MOSI, respectively. Connected with ~4" wires terminated with 1-pin female Dupont. Let me know if you need any more details!
Edit: Swapped probe
Swapped probes 3 and 4 on the PCB side. Noise does not follow the probe; it only appears on the MISO line.