I'm considering a design which has multiple PIC-based controllers producing PWM signals at 31 kHz. Sometimes, under a well-defined "handover" condition, some pair of PWM power feeds will be connected together (with the same duty-cycle) and need to be driven together. The power feeds come from L6206 H-Bridge drivers, which themselves introduce a 0.5-1 \$\mu\$s dead-time on a transition. But during the handover, I need those PWM signals accurately sync'd so that they don't fight each other.

If I can synchronize the two PICs' PWM generator timers to within 0.5 \$\mu \$s, then I think this will work OK. The PICs are running at 32 MHz from their internal HFINTOSC oscillators and are I2C slaves (over maybe 1 metre via two connector hops) to a master controller which manages the PWM levels, enable/disable etc.

It's easy to run a signal to all controllers, such as a 1 ms stable synchronization clock, which could trigger a low-latency interrupt. Then I can write a primitive phase-locked loop to tweak OSCTUNE and basically keep all the PWM counter clocks in sync.

I've read other questions about synchronizing microcontrollers and I'm super-lucky that I'm not trying to do it over Bluetooth or similar; I can have a physical sync' wire!

But my concern is: are the PIC internal oscillators stable enough over the course of a millisecond or so to not drift apart by more than a fraction of a microsecond?

The datasheet indicates that the oscillator is stable to +/-2 % over a temperature range and the power supply to the PICs will be common and smooth. So I don't see these varying much over a period of milliseconds or even minutes. But can I rely on its jitter to be within 500 ppm? If not, the PLL will always be fighting the wandering clock...

Further progress: We've implemented the sync pulse system as indicated in the question, though it pulses every 256 μs rather than every 1 ms, to reduce jitter. The recorded jitter is around +/-400 ns for the devices we've tried, so that's within spec'.

We have capacity to decrease the pulse gap to 32 μs but we're still experimenting. More news will follow.

  • 2
    \$\begingroup\$ Why are you insisting on using the internal oscillators? Why not just run them all from a common external oscillator? \$\endgroup\$
    – Dave Tweed
    Commented Mar 21, 2020 at 13:46
  • \$\begingroup\$ @DaveTweed I'm wondering about that - I'd have to run 8MHz around an estate that's perhaps a metre or so across, and over two connectors. I'll add that constraint to the question. But that is a possible solution, thanks! \$\endgroup\$
    – SusanW
    Commented Mar 21, 2020 at 14:02
  • \$\begingroup\$ Which PICs are you using? \$\endgroup\$ Commented Apr 19, 2020 at 20:33
  • \$\begingroup\$ @BruceAbbott it's the PIC16F15356 \$\endgroup\$
    – SusanW
    Commented Apr 19, 2020 at 20:43

1 Answer 1


Read about disciplined oscillators.

Some MCUs allow to lock the internal clock to an external signal (say 10KHz), saving you the circuit to upscale that clock.

You would need to distribute that signal (would RF be acceptable?)

If you don't want to distribute your own synchronization signal, GPS might be an alternative.

GPS distributes a 1PPS signal. You could buy a GPSDO or make your own through PLL or FLL circuits and a GPS module.


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