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I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that

We now examine a simple example, shown in Figure 8-2, where both the launch and capture flip-flops have the same clock. The first rising edge of clock CLKM appears at time Tlaunch at launch flip-flop. The data launched by this clock edge appears at time T launch + T ck2q + Tdp at the D pin of the flip-flop UFF1. The second rising edge of the clock (setup is normally checked after one cycle) appears at time Tcycle + Tcapture at the clock pin of the capture flip-flop UFF1.

Why is he saying that "setup is normally checked after one clock cycle"?

Why can't we consider the clock before the very next active edge?

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  • \$\begingroup\$ why is he saying that "setup is normally checked after one clock cycle"?. Why can't we consider the clock at the very next active edge?.. Aren't they same, checked after one clock cylce of launch edge or very next active edge of launch edge. \$\endgroup\$ – RAMA KRISHNA MEDA Mar 22 at 5:57
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When you consider the clock before the very next active edge, you're doing hold time check.

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