# Problem in understanding how LM565 increases the VCO frequency

We were tinkering with an LM565 (PLL IC) in school and I noticed that despite the fact that the maximum frequency of VCO was 3.5 kHz, I was able to use the PLL up to circa 5 kHz with the free running frequency of VCO set to 2 kHz.

Can someone please help me with understanding why this is possible? I think that if someone explains how the oscillator gets the additional current to go beyond 2 kHz (which was the free-running frequency of VCO,) then going even beyond 3.5 kHz should be self-explanatory.

In the attached schematic of LM565:

1. is a Gilbert cell phase detector - PHASE DETECTOR,
2. is bias current generator for current sources,
3. is amplifier - AMP,
4. is responsible for charging and discharging the timing capacitor,
5. is responsible for the measurement and amplification of capacitor voltage,
6. is responsible for controlling discharging of the cap,
7. is bias voltage generator for differential pair in upper 6, that triggers the (dis)charging process.

I see only one way of affecting the frequency (current through timing capacitor) – by the amplifier in block number 3 – the input of Q12.

I have trouble in understanding how Q12 may affect the current. Even the simulation of this circuit (mainly Q12) poses a challenge.

What do you think? Have I made a mistake in understanding this circuit? I am still a beginner, so please point out any mistakes in my reasoning that I have made :).

To achieve a 50% duty cycle at the output, charging and discharging the capacitor should take the same amount of time.

This is the internal diagram of LM565: This is the schematic that we used to test LM565: This is the LM565 datasheet

• Are you sure about the max VCO freuquency? In the datasheet it is something around 500kHz. – vtolentino Mar 24 at 10:42
• I know that the LM565 can achieve pretty high frequency on the VCO, but it was configured to generate relatively low frequency for ease of measurement and ease of understanding how things work. The module that we tested had fixed resistors and capacitors, so we couldn't change the parameters. The frequency rage was decided by the manufacturer of said module. – KamilWitek Mar 24 at 10:47
• Could you please point out where you got the idea that the maximum frequency of the VCO is 3.5kHz? I see a lot of references to the VCO in the datasheet, but nothing about 3.5kHz. In fact, the datasheet explicitly says that the maximum VCO operating frequency is well over 200kHz. – JRE Mar 24 at 11:01
• The maximum frequency with the timing resistor turned way down (5 kΩ) and the timing capacitor being 100 nF is circa 3.5 kHz :). Changing the capacitor to 10 nF yields a maximum frequency of 36.6 kHz, if I remember correctly. So it's component-dependent. – KamilWitek Mar 24 at 11:31

I have trouble in understanding how Q12 may affect the current.

The base voltage on Q12, together with Q13, establishes a voltage across the external timing resistor, creating a current source that charges the timing capacitor.

IIRC, the circuit in the bottom half of block #4 is a current sink that operates at 2× the current set by the top half, so when Q23 switches on, the capacitor discharges at a net current that is essentially equal to the charging current.

• OK, so basically it seems, that when the PLL was open, both inputs (2,3) were at the same potential, so Gilbert cell created the same potential at bases Q10 and Q11 which in turn balanced differential pair amplifier in block 3, which in turn created a stable current through Q12, so stable (dis)charging current for capacitor, and gave me this range: 50 Hz to 3.5 kHz (which was a kind of fine adjustment provided by VR1). When the input signal was applied, the current through Q12 increased, which in turn increased the charging current even more, which was responsible for the higher frequency. – KamilWitek Mar 24 at 12:25
• Is that right, or am I missing something? – KamilWitek Mar 24 at 12:25
• Yes, that's pretty much it. – Dave Tweed Mar 24 at 12:39
• I shouldn't write such comments, but thanks ❤️ :) – KamilWitek Mar 24 at 12:46

Before going deep into the circuit, maybe a basic understanding of how a PLL works might be helpful. The PLL consists basically of 3 blocks: 1. Phase detector 2. Filter 3. VCO

How it works: Upon applying a frequency to its input, the phase difference between this signal and the free-running frequency will be measured (phase error). The phase error is then filtered and used to readjust the VCO in order to reduce the error via a negative feedback. The PLL is limited when it comes to the "maximum phase error" it can measure. Putting it simply, if the input frequency is way larger or smaller than the free-running frequency, it will not be able to calculate the phase error. This limitation is usually stated as capture range, which basically means for what frequency range the PLL's free-running frequency can lock to (reduce error to ~ zero). Once the PLL is locked, there is another frequency range (usually larger) which determines the frequencies for which the PLL will remain locked (aka Hold-in range).

According to the datasheet: It means, that for a free-running frequency = 2kHz, the PLL should be able to remain locked to frequencies :

$$f_{upper}= f_{free} + \frac{8\cdot 2kHz}{10V} = 2kHz + 1.6kHz = 3.6kHz$$

P.S.: I might have overseen it, but I could not find any information about the capture range.

• OK, but Vc = (V+) + |V-| = 10 V, not 5 V. So, plugging those numbers to the equation mentioned above yields a f_upper of 3.6 kHz. – KamilWitek Mar 24 at 11:36
• At the input frequency equal to 4.84 kHz the phase difference was close to 0 degrees. – KamilWitek Mar 24 at 11:38
• It seems a bit strange. Were you measuring with an osci the VCO frequency and the input frequency simulatenously? – vtolentino Mar 24 at 11:47
• Yes, that what I have done. I think, that my comment under (and with) Dave Tweed's answer is the reason why this seems strange. – KamilWitek Mar 24 at 12:54