We were tinkering with an LM565 (PLL IC) in school and I noticed that despite the fact that the maximum frequency of VCO was 3.5 kHz, I was able to use the PLL up to circa 5 kHz with the free running frequency of VCO set to 2 kHz.
Can someone please help me with understanding why this is possible? I think that if someone explains how the oscillator gets the additional current to go beyond 2 kHz (which was the free-running frequency of VCO,) then going even beyond 3.5 kHz should be self-explanatory.
In the attached schematic of LM565:
- is a Gilbert cell phase detector - PHASE DETECTOR,
- is bias current generator for current sources,
- is amplifier - AMP,
- is responsible for charging and discharging the timing capacitor,
- is responsible for the measurement and amplification of capacitor voltage,
- is responsible for controlling discharging of the cap,
- is bias voltage generator for differential pair in upper 6, that triggers the (dis)charging process.
I see only one way of affecting the frequency (current through timing capacitor) – by the amplifier in block number 3 – the input of Q12.
I have trouble in understanding how Q12 may affect the current. Even the simulation of this circuit (mainly Q12) poses a challenge.
What do you think? Have I made a mistake in understanding this circuit? I am still a beginner, so please point out any mistakes in my reasoning that I have made :).
To achieve a 50% duty cycle at the output, charging and discharging the capacitor should take the same amount of time.
This is the internal diagram of LM565:
This is the schematic that we used to test LM565: