I want to see how certain algorithm would fit FPGA architecture and plan to implement it with HLS tool like CλaSH which produces VHDL/Verilog. All I know about FPGAs so far is it's an array of interconnected logic blocks. So I wonder how can I ensure it's gonna be possible at all since every code construct consumes a certain amount of logic blocks of FPGA and it simply might not have enough of it?
For example when developing an algorithm for CPU prior to even trying to run it you need to ensure that it will have enough memory to load the code. It's never the problem with modern PCs anymore but it's very tight with FPGAs, right?
Is there a way to determine how much logic blocks an implementation requires prior to running it (... purchasing a dev board)? Are there any other considerations needed to be accounted for like logic blocks array width/length (which determine the flow parallelism?), etc?