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Back in the mists of time when I started coding, at least as far as I'm aware, processors all used a fixed amount of power. There was no such thing as a processor being "idle".

These days there are all sorts of technologies for reducing power usage when the processor is not very busy, mostly by dynamically reducing the clock rate.

My question is why does running at a lower clock rate use less power?

My mental picture of a processor is of a reference voltage (say 5V) representing a binary 1, and 0V representing 0. Therefore I tend to think of of a constant 5V being applied across the entire chip, with the various logic gates disconnecting this voltage when "off", meaning a constant amount of power is being used. The rate at which these gates are turned on and off seems to have no relation to the power used.

I have no doubt this is a hopelessly naive picture, but I am no electrical engineer. Can someone explain what's really going on with frequency scaling, and how it saves power. Are there any other ways that a processor uses more or less power depending on state? eg Does it use more power if more gates are open?

How are mobile / low power processors different from their desktop cousins? Are they just simpler (less transistors?), or is there some other fundamental design difference?

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    \$\begingroup\$ You're wrong, processors never used the same amount of power over time, it was always variable. Simplifying things significantly, one can assume that power is only spent on switching a single flip-flop value. Therefore, the more computation is performed per second, the more internal registers change their values, the more power is spent. \$\endgroup\$
    – SK-logic
    Commented Nov 12, 2012 at 9:10
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    \$\begingroup\$ If I remember my electronics correctly, most of the "wasted" energy (a.k.a "heat") is leakage (a.k.a. (small) amounts of current flowing where no flow should happen). That happens more when you're a.) using a higher voltage and b.) switching at higher frequencies. Most modern CPUs reduce both the voltage and the frequency in their low-power states (and even if they reduce just one of those, it's still a gain). \$\endgroup\$
    – Joachim Sauer
    Commented Nov 12, 2012 at 9:47
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    \$\begingroup\$ @SK-logic: Many historic processors use ECL logic, which consumes roughly the same amount of power no matter what the clock rate. Seymour Cray designed the CDC 8600, the Cray-1, the Cray X-MP, the Cray Y-MP, the Cray T90 to use ECL. The Wikipedia ECL logic article lists a few more from other companies. Are you saying those machines never existed, or are you saying they don't count as processors? \$\endgroup\$
    – davidcary
    Commented Mar 15, 2016 at 18:28
  • \$\begingroup\$ The processors also save power by using a halt instruction. The operating system kernel can set a timer to wake up the processor and execute that instruction to make the processor fall asleep. \$\endgroup\$
    – Oskar Skog
    Commented Apr 20, 2017 at 12:51

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The rate at which these gates are turned on and off seems to have no relation to the power used.

This is where you are wrong. Basically, each gate is a capacitor with an incredibly tiny capacitance. Switching it on and off by "connecting" and "disconnecting" the voltage moves an incredibly tiny electrical charge into or out of the gate - that's what makes it act differently.

And a moving electrical charge is a current, which uses power. All those tiny currents from billions of gates being switched billions of times per second add up quite a bit.

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  • \$\begingroup\$ That's what's happening in memory - DRAM memory. The memory from the processor (the cache) uses SRAM which is not implemented with capacitors... \$\endgroup\$
    – m3th0dman
    Commented Nov 12, 2012 at 14:05
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    \$\begingroup\$ @m3th0dman: I am not talking about elementes intended to be capacitors. Every transistor, every element inside the CPU has a capacitance. \$\endgroup\$
    – Michael Borgwardt
    Commented Nov 12, 2012 at 14:49
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As SK-logic's comment points out most power is really spent on switching flip-flop rather than a steady state.

For dynamically reducing there are two main things you can do IIRC.

  1. if whole areas of a chip are not being clocked you can potentially turn off the power for those areas completely

  2. The clock tree itself is one of the largest power drains in the system, largely as it is the fastest switching part of a system. So reducing the power in the clock tree itself is significant.

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  • \$\begingroup\$ What is the clock tree? \$\endgroup\$
    – akaltar
    Commented Sep 9, 2016 at 15:37
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    \$\begingroup\$ @akaltar the total of all lines that distribute the clock signal to every element of the processor that needs to be synchronized with the clock. \$\endgroup\$
    – Michael Borgwardt
    Commented Mar 7, 2017 at 15:30
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The power consumed by an electronic circuit has two components:

  • the leakage, which is more or less independent of the frequency constant and will depend on the technology and working voltage;
  • the switching power, which depends on the frequency (it's due to loading and unloading various capacitances, transistors and wires)

In order to reduce consumption, processor designers use several techniques:

  • modifying the frequency depending on the load (this will act only on the switching power)
  • reducing the power or even powering off parts of the circuits when they aren't needed

These techniques have as a result that depending on your load, you may be better off, from the power consumption POV, either reducing the frequency or doing a "sprint" at full speed and then cutting out a subset of the circuits.

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  • \$\begingroup\$ It is also possible that reducing frequency allows to reduce the operating voltage (because transistors are a bit slower then) to reduce leakage. \$\endgroup\$
    – Grabul
    Commented Sep 9, 2016 at 21:06
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Running at a lower clock rate does not affect the energy required to perform a fixed task. It might even increase the energy required if you account for leakage, and are able to switch off entirely.

Where a lower clock rate does save energy is in also being able to reduce the operating voltage. Reducing voltage often saves enough power to compensate for needing to remain active for longer.

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  • \$\begingroup\$ I don't agree Sean. Lowering the clock rate reduces all of the parasitic switching losses involved in the entire clock-chain, which is massive in a typical CPU. My Atom netbook runs at 1GHz, if I throttle the CPU down to 500MHz it runs cooler and visibly draws less power from from the supply, and it does affect the task - it takes twice as long to complete. \$\endgroup\$
    – rdtsc
    Commented Sep 9, 2016 at 15:33
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    \$\begingroup\$ @rdtsc Careful now. Sean writes energy, not power. \$\endgroup\$
    – pipe
    Commented Sep 9, 2016 at 15:36
  • \$\begingroup\$ @rdtsc You're confusing power and energy. First order, a specific task will require a fixed number of clock cycles. Think about how a battery will respond to your task at the two different operating points. \$\endgroup\$
    – Sean Houlihane
    Commented Sep 9, 2016 at 15:37
  • \$\begingroup\$ Ahh yes. Still working on first cup of coffee here. :) I'd have to measure it, but I think the energy used will actually be slightly more with a lower clock rate, since a modern CPU has so many periodic events to handle per second. There will be more of these for a slower clock, and more means a longer time to task completion. \$\endgroup\$
    – rdtsc
    Commented Sep 9, 2016 at 15:41
  • \$\begingroup\$ Some related background reading anandtech.com/show/9330/exynos-7420-deep-dive/6 \$\endgroup\$
    – Sean Houlihane
    Commented Sep 9, 2016 at 15:54

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