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I need to design a sequence detector which detects 0110 or 0010. If any of this is received, the output is logically correct and gives 1. Here is my attempt so far. I would appreciate some advice because I am not sure if it is correct.

enter image description here

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    \$\begingroup\$ What range of numbers are possible? \$\endgroup\$
    – Andy aka
    Mar 25, 2020 at 12:41
  • \$\begingroup\$ How do you mean what range? \$\endgroup\$
    – Ella
    Mar 25, 2020 at 12:44
  • \$\begingroup\$ List the invalid numbers. \$\endgroup\$
    – Andy aka
    Mar 25, 2020 at 13:13
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    \$\begingroup\$ What happens at the end of the 4-bit sequence? Is 000110 valid after the 6th bit time or after 000 do you need to wait for a new "start" signal or something before starting again? \$\endgroup\$
    – user16324
    Mar 25, 2020 at 13:16
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    \$\begingroup\$ what type of sequence_detector ,is it overlapping or non_overlapping sequence detector you are trying to draw. \$\endgroup\$ Mar 27, 2020 at 3:34

1 Answer 1

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This is an overlapping sequence-detector for the required sequences. I used this website to draw the FSM.

enter image description here

This is the code I have written to draw it:

#states
START
SEEN_0
SEEN_00
SEEN_01
SEEN_0x1
SEEN_0011
SEEN_0110
#initial
START
#accepting
START
SEEN_0
SEEN_00
SEEN_01
SEEN_0x1
SEEN_0011
SEEN_0110
#alphabet
input_0
input_1
#transitions
START:input_0>SEEN_0
START:input_1>START
SEEN_00:input_0>SEEN_00
SEEN_00:input_1>SEEN_0x1
SEEN_01:input_0>SEEN_0
SEEN_01:input_1>SEEN_0x1
SEEN_0x1:input_0>SEEN_0110
SEEN_0x1:input_1>SEEN_0011
SEEN_0110:input_0>SEEN_0
SEEN_0110:input_1>SEEN_01
SEEN_0011:input_0>SEEN_0
SEEN_0011:input_1>START
SEEN_0:input_0>SEEN_00
SEEN_0:input_1>SEEN_01
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