How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. Show timing of one loop cycle in Table below.
This is the question and here is the answer in the second photo however I didn't understand how we got the number of clock cycles for segment execution on pipelined processor. My doctor solved it in this way:
Number of cycles in the loop = 15 c.c.
Number of clock cycles for segment execution on pipelined processor =
= 1 c.c. (IF stage of the initial instruction) + (Number of clock cycles in the loop L1) x
Number of loop cycles = 1 + 15 x 400/4 = 1501 c.c.
Speedup of the pipelined processor comparing with non-pipelined processor =
= Number of Clock cycles for the segment execution on non-pipelined processor /
Number of Clock cycles for the segment execution on simple pipelined processor =
= 3005 c.c. / 1501 = 2 times
Can you please explain me from where did we get the 1? What is the formula he used?