I'm working on a simulation of an RISC-V cpu (in Logisim-Evolution, not the best, I know). But now, I have almost finished designing it (and so far it works like a charm), and now it is time to build it. (I have build and tested about 80% of my project so far) The issue I'm facing now, is how to design and build the Immediate Generator . This is my Immediate generator in Logisim-Evolution:
It works just fine, decoding every type of instruction in RISC-V (RV32I). But the problem is from which parts i should build it. The immediate encodings in RISC-V are sometimes tangled (like the UJ type or SB type), but I understand why. What they wanted to achieve is to use as few wires as possible, thus saving space. But, in my situation, I don't know how this could help me. My idea was that I would use 74HCT245 in TSSOP20 package (i have about 70 of them around me) to just simply wire each encoding type and then use the buffers (74HCT245) to act like an MUX (as shown in first picture). This leads to 5 * 4 = 20 ICs. This isn't a very lot, but this would be large on a 2 layer PCB. Can we optimize it a little more? Maybe how they intended? Should i use different ICs?
EDIT 1: My design constrains:
- build it using commonly found ICs (gates, plexers, etc..) not FPGAs, PlAs.
- build it as small as possible :) (It needs to fit on 2 layer PCB 10*10cm MAX)