I'm working on a simulation of an RISC-V cpu (in Logisim-Evolution, not the best, I know). But now, I have almost finished designing it (and so far it works like a charm), and now it is time to build it. (I have build and tested about 80% of my project so far) The issue I'm facing now, is how to design and build the Immediate Generator . This is my Immediate generator in Logisim-Evolution:

enter image description here

It works just fine, decoding every type of instruction in RISC-V (RV32I). But the problem is from which parts i should build it. The immediate encodings in RISC-V are sometimes tangled (like the UJ type or SB type), but I understand why. What they wanted to achieve is to use as few wires as possible, thus saving space. But, in my situation, I don't know how this could help me. My idea was that I would use 74HCT245 in TSSOP20 package (i have about 70 of them around me) to just simply wire each encoding type and then use the buffers (74HCT245) to act like an MUX (as shown in first picture). This leads to 5 * 4 = 20 ICs. This isn't a very lot, but this would be large on a 2 layer PCB. Can we optimize it a little more? Maybe how they intended? Should i use different ICs?

EDIT 1: My design constrains:

  • build it using commonly found ICs (gates, plexers, etc..) not FPGAs, PlAs.
  • build it as small as possible :) (It needs to fit on 2 layer PCB 10*10cm MAX)
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    \$\begingroup\$ what are your design constraints? "can we optimize it a little" sounds a lot like, yes, we can, by throwing out the discrete ICs and just putting your design on an FPGA, but I get the feeling that's not what you want. However, I can't tell from your question what you actually want, so it's hard to advise. \$\endgroup\$ – Marcus Müller Mar 26 '20 at 11:24
  • \$\begingroup\$ Also, 80 muxes sounds like way too few for a full RISC decoder stage, but I'm willing to believe you! (also, not quite sure how your idea of converting bus transceivers to muxes would work, but I believe you that you do.) \$\endgroup\$ – Marcus Müller Mar 26 '20 at 11:24
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    \$\begingroup\$ @MarcusMüller I'm now just focusing on the immediate generator unit, the instruction decoder stage is mostly done by EEPROMs. My goal is to build it without FPGAs (PLAs and others) but on mostly TTL logic and EEPROMs (like I said, i have almost everything done, including ALU (yes, EEPROMs), shifter unit, memory, register file..) but this is one of last remaining modules on my list. The MUX form bus transcievers is simple (kind of): connecting outputs of every transciever and than selecting which "stage" should get activated. \$\endgroup\$ – Kralik_011 Mar 26 '20 at 12:03
  • \$\begingroup\$ woah, 10×10cm with two layers?! that's ambitious! \$\endgroup\$ – Marcus Müller Mar 26 '20 at 13:29
  • \$\begingroup\$ @MarcusMüller Well i meant that this circuit needs to fit the 10*10cm area :). Every module is on separate 10*10 panel, It would be impossible to wire the whole PCU on 10 by 10cm. In case the memory unit, I've managed to fit and route 49 Ics on that area, so I'm pretty confident that this could fit! :) \$\endgroup\$ – Kralik_011 Mar 26 '20 at 13:49

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