# Logical Effort Inverter Sizing

I'm currently trying to size some logic inverters (CMOS IC Inverters, not power converison) based on the Logical Effort Approach. This approach requires that you know the input capacitance of an x1 size inverter.

I've run a DC operating point simulation in Cadence Virtuoso and selected the DC parameters of my PMOS and NMOS device of my x1 inverter. However, there are so many capacitances that it shows, some don't make complete sense to me.

For example, there is Cgd and there is also Cdg are they are different values, how does that make sense?

In short, which capacitances do I sum up to find my total input capacitance for use in my logical effort equations?

• What is the logical effort approach? What is an x1 size inverter? Mar 26, 2020 at 19:05
• @Hearth It's an approach to size gates in an optimum fashion. A x1 size inverter can be any size of PMOS and NMOS devices, it's the base size, after which x2 and x4, etc. inverters are based off of. The question is really just focussed on how determine the input capacitance of a MOSFET via Cadence given all of the different parasitics that Cadence reports. Mar 26, 2020 at 19:12
• bibl.ica.jku.at/dc/build/html/logicaleffort/logicaleffort.html Mar 26, 2020 at 19:13
• Be aware that the term "inverter" is also used to describe a device to generate AC power from a DC source and frequently discussed here. You might copy some of the information from your comment above into the question for clarity. Mar 26, 2020 at 19:14
• $C_{gd} = \dfrac{dQ_g}{dV_d}$, $C_{dg} = \dfrac{dQ_d}{dV_g}$ Mar 26, 2020 at 19:38

It's hard to calculate the total effective capacitance from model parameters because the capacitance from the gate to body of each transistor will change as $$\V_{GS}\$$ changes and the inversion layer forms.
$$C = i \times \frac{dt}{dV}$$
where $$\i\$$ is the constant current, $$\dt\$$ is the time for the input voltage change, and $$\dV\$$ is the magnitude of the voltage change (usually just equal to $$\V_{DD}\$$).