# A conflicting result in the diode and capacitor circuit

Consider following circuit: simulate this circuit – Schematic created using CircuitLab

The question is determining output voltage. D1 is an ideal diode with zero threshold voltage.

Certainly when input goes from zero to peak voltage the diode is off but the problem is after that time. Both on and off assumptions for the diode is valid when $$T/4\le t\le T/2$$ If we assume diode is off then $$V_D = 0 - V_{out} = -V_1\lt 0$$ because $$T/4\le t\le T/2 \implies 0\le V_1\le V_{peak}$$ On the other hand assuming diode is on leads to $$i_D = -C_1V_1' \gt 0 \implies V_1'\lt 0$$ which is true because $$V_1' = V_p\omega \cos{\omega t} \ \ \ \ and \ \ \ T/4\le t\le T/2$$ What is my mistake here? According to my book during entire positive half cycle diode is off but I don't know what's the problem with on state.

• @DKNguyen i_D is the current of diode which goes from anode to cathode. Mar 27, 2020 at 2:09
• I'm talking about the passive sign convention in your second equation. Why is Vd=-Vout? I don't know what CV in your 4rth equation is supposed to be either. CV doesn't mean anything. Caps aren't resistors. Mar 27, 2020 at 2:10
• C1V1 is not what the capacitor equation is. i=C(dv/dt) for a capacitor Mar 27, 2020 at 2:16
• "If we assume diode is off then..." - Why wouldn't it be? The diode was off so the capacitor got no charge and voltage is the same on both sides, therefore the diode stays off. Nothing changes until V1 goes negative, when the diode turns on and charges the capacitor. Mar 27, 2020 at 3:19
• @user215805 Note that cos(2pi*(1/T)*(T/4)) = cos(pi/2) = 0 and cos(2pi*(1/T)*(T/2)) = cos(pi) = -1. Nov 10, 2020 at 7:49

I think the problem here is your on-state assumption, because it contradicts itself

See, according to the following statement:

$$i_D=−C_1V_1^′>0$$

It's assumed that $$\i_D=−C_1V_1^′\$$, meaning that the current flows from the cathode end to the anode end of the diode. Putting it simply, the $$\i_D\$$ arrow in your drawing is flipped. This assumption in itself is OK. It means that the calculated current will have an opposite direction.

The problem starts though with the second part of your assumption, i.e. $$\i_D>0\$$: This opposes the assumption that you just made (negative $$\i_D\$$). You cannot have both assumptions at the same time, because they just contradict each other.

The correct assumption in this case would be

$$i_D=−C_1V_1^′ < 0 \rightarrow V_1^′>0$$

OR if you flip the $$\i_D\$$ arrow, you would have

$$i_D=C_1V_1^′>0 \rightarrow V_1^′>0$$

which is the same. Considering the derivative of the voltage across the capacitor:

$$V_1^′=V_p\omega \cos(\omega t)$$

Selecting a few time points, a frequency of $$\100Hz\$$ and $$\C_1=1\mu F\$$ (considering the original arrow direction) yields:

$$i_D(t=T/4)=-C_1\cdot V_p\omega \cos(\omega t)=-1\mu F\cdot 1V\cdot 2\pi 100Hz \cos(\frac{\pi}{2})=0A$$

$$i_D(t=3T/8)=444\mu A$$

$$i_D(t=T/2)=628\mu A$$

This can be double checked via simulation

Simulating the on-state assumption (diode with no forward voltage and negligible off-resistance - otherwise no current could flow):

As you can see from the waveform, the current values match the calculated ones. In this case, the current is indeed flowing from the cathode to the anode, meaning that the assumption is correct.  • Why you are saying that $i_D=−C_1V_1^′$, means the current flows from the cathode end to the anode end of the diode? Apr 2, 2020 at 17:13
• When you analyze a circuit using KCL, you have to select a direction for the current. In your case the arrow is pointing upwards, meaning the current is flowing from the cathode to the anode side of the diode. Apr 2, 2020 at 17:28
• Yes, that's right. We choose a direction for the current but it can be positive or negative. Here we assume that diode is on and then choose a direction for iD(It doesn't mean iD > 0 necessarily). Using KVL $$i_D = -C_1V_1'$$ For the diode to be on means $$i_D \gt 0$$ so $$V_1' \lt 0$$. Apr 2, 2020 at 17:38
• This is contradictory. You cannot say at the same time $i_D=-C_1V_1^′$ and $i_D>0$. In the first assumption you say that the current flows from cathode to anode, meaning it is going to be negative. And in your second assumption you assume that it flows from anode to cathode (positive). Positive and negative refer to the direction of the $i_D$ arrow Apr 2, 2020 at 17:44
• After choosing a direction for iD and applying KVL we got that equation. No further assumptions was made for iD. Apr 2, 2020 at 17:51

The diode on/off trial method may not always work if there is a capacitor in the circuit, it could conduct for part of each cycle. But, for now, lets assume that it will work.

First, solve for steady-state only, don't worry about startup. At steady-state, the diode must be off, else the capacitor would charge to infinity (there is no other path for the diode current).

Next, recognize that the cap is a high-pass filter. Since there is no resistor (infinitely large), the cutoff frequency is infinitely low, it will pass everything but DC.

There is no current in the diode at steady-state (previously concluded), but the diode also won't let the output voltage go below zero.

High-pass filter, voltage never below zero: conclusion: sine, with bottom of sine at zero.

If you must know what happens for the first cycle(s), you need to analyze in pieces.

For 0 ≤ t ≤ T/2, diode is off.

For T/2 ≤ t ≤ 3T/4, diode is on, cap charges to Vpeak.

For 3T/4 ≤ t, diode is off.

Here is the answer using the simulator: simulate this circuit – Schematic created using CircuitLab I modified the diode parameters to make it close to perfect. You can see what I did in this answer. Simple circuit transfer function and output graph

• Thanks for your answer. Could you mention what's my mistake in the above analysis please? Mar 27, 2020 at 12:39
• The derivative of sine (cos) is only valid if the voltage across the cap is a sine. It won't be until the circuit reaches steady-state.. Mar 27, 2020 at 13:53
• If we assume that diode is on then voltage across the cap is a sine. Mar 27, 2020 at 15:53
• Besides the steady-state issue, cosine is negative from T/4 to T/2, so current can't flow through the diode. Mar 27, 2020 at 16:10
• Yes, it's negative so i_D>0 because $$i_D = -C_1V_1' \gt 0$$ Mar 27, 2020 at 16:13

When you assume the diode states than you need to ensure that there are no contradictions in the resulting circuit configuration. By just looking at the I-V characteristics of diode it seems like the ON state is possible but the resulting circuit does not follow KVL.
For the current direction you assumed, the voltage drop across the loop is $$\V_1 - V_c > 0\$$, since $$\V_c < 0\$$.
There are no contradictions associated with the OFF state and hence it is the correct state.
EDIT
The circuit diagram on the left shows you the original circuit which is transformed to circuit on the right if diode is assumed to be on. For diode to be ON, the current has to flow in the indicated direction. This implies the capacitor plate connected to node $$\V_{out}\$$ will be positively charged by the current. Consequently, the voltage drop across the capacitor $$\V_c\$$, as indicated below, will be positive (I have reversed the polarity of $$\V_c\$$ from from what you indicated). Now, apply KVL in the A - B - $$\V_{out}\$$ - D loop: $$0 + V_s + V_c + V_d = 0 \implies V_s + V_c = 0$$. This is a contradiction since both $$\V_s\$$ and $$\V_c\$$ are positive as explained before.
But even before solving for these equations, you can see that if you have the circuit on the right the current will flow from the voltage source towards the ground not the other way around, which you indicated. Since diode does not allow such a current, it will be turned off. simulate this circuit – Schematic created using CircuitLab

• Why ON state does not follow KVL? Here is the main problem. Mar 29, 2020 at 13:25
• As I explained in the answer, the capacitor will be charged in the opposite polarity to what you depict in the figure. The potentials of voltage source and capacitor are going to add up giving non-zero potential drop across the loop because the diode is a short. This is the contradiction. Mar 29, 2020 at 13:33
• I think the reason is Vc(0+) = Vc(0-) = 0. Is this same as your answer? Mar 29, 2020 at 13:41
• No...hopefully the edit helps Mar 29, 2020 at 14:29

It's quite simple: the assumption the diode is in forward mode is incorrect.

Certainly when input goes from zero to peak voltage the diode is off

Correct. No current flows through the capacitor and diode.
Therefore $$\V_{out}(t) = V_1(t)\$$ for $$\ 0 \le t\le T/4 \$$.

Both on and off assumptions for the diode is valid when $$T/4\le t\le T/2$$

This statement is incorrect. As we saw above, at $$\t = T/4\$$ applies: $$\V_{out}=V_1(T/4) = V_{peak} \$$.
Therefore $$\V_D=0-V_{peak}\$$, so it is, or better, it stays reversed biased.
In other words, only "the off assumption for the diode" is true.

Note that $$i_D = -C\frac{d \Big(V_1(t)-Vout(t) \Big)}{dt} = 0 \neq -C_1V_1'$$

Note that when $$\V_{out}(T/4)=0\$$ were true, then the remainder of your elaboration is true (I inserted a part):

$$i_D = -C\frac{d \Big(V_1(t)-Vout(t) \Big)}{dt} = -C_1V_1' \gt 0 \implies V_1'\lt 0$$ which is true because $$V_1' = V_p\omega \cos{\omega t} \ \ \ \ and \ \ \ T/4\le t\le T/2$$

Your problem is that is some inappropriate cases, you used V1 as the voltage across the cap. In fact, isn't V1, it's V1-Vout

• Sorry but I couldn't understand your answer. Could you please elaborate? Mar 27, 2020 at 15:51

Vout will be a sinewave with its negative going troughs peaking at 0V and its positive going peaks peaking at 2*root2*V1 where V1 is the RMS value of the voltage source.

The +ve and -ve signs on the cap are the wrong way around.