A conflicting result in the diode and capacitor circuit

Question

Consider following circuit:

^{simulate this circuit – Schematic created using CircuitLab}

The question is determining output voltage. D1 is an ideal diode with zero threshold voltage.

Certainly when input goes from zero to peak voltage the diode is off but the problem is after that time. Both on and off assumptions for the diode is valid when $$T/4\le t\le T/2$$ If we assume diode is off then $$V_D = 0 - V_{out} = -V_1\lt 0$$ because $$T/4\le t\le T/2 \implies 0\le V_1\le V_{peak}$$ On the other hand assuming diode is on leads to $$ i_D = -C_1V_1' \gt 0 \implies V_1'\lt 0$$ which is true because $$V_1' = V_p\omega \cos{\omega t} \ \ \ \ and \ \ \ T/4\le t\le T/2$$ What is my mistake here? According to my book during entire positive half cycle diode is off but I don't know what's the problem with on state.

Answer 1

I think the problem here is your on-state assumption, because it contradicts itself

See, according to the following statement:

$$i_D=−C_1V_1^′>0$$

It's assumed that \$i_D=−C_1V_1^′\$, meaning that the current flows from the cathode end to the anode end of the diode. Putting it simply, the \$i_D\$ arrow in your drawing is flipped. This assumption in itself is OK. It means that the calculated current will have an opposite direction.

The problem starts though with the second part of your assumption, i.e. \$i_D>0\$: This opposes the assumption that you just made (negative \$i_D\$). You cannot have both assumptions at the same time, because they just contradict each other.

The correct assumption in this case would be

$$i_D=−C_1V_1^′ < 0 \rightarrow V_1^′>0$$

OR if you flip the \$i_D\$ arrow, you would have

$$i_D=C_1V_1^′>0 \rightarrow V_1^′>0$$

which is the same. Considering the derivative of the voltage across the capacitor:

$$V_1^′=V_p\omega \cos(\omega t)$$

Selecting a few time points, a frequency of \$100Hz\$ and \$C_1=1\mu F\$ (considering the original arrow direction) yields:

$$i_D(t=T/4)=-C_1\cdot V_p\omega \cos(\omega t)=-1\mu F\cdot 1V\cdot 2\pi 100Hz \cos(\frac{\pi}{2})=0A$$

$$i_D(t=3T/8)=444\mu A$$

$$i_D(t=T/2)=628\mu A$$

This can be double checked via simulation

Simulating the on-state assumption (diode with no forward voltage and negligible off-resistance - otherwise no current could flow):

As you can see from the waveform, the current values match the calculated ones. In this case, the current is indeed flowing from the cathode to the anode, meaning that the assumption is correct.

Answer 2

The diode on/off trial method may not always work if there is a capacitor in the circuit, it could conduct for part of each cycle. But, for now, lets assume that it will work.

First, solve for steady-state only, don't worry about startup. At steady-state, the diode must be off, else the capacitor would charge to infinity (there is no other path for the diode current).

Next, recognize that the cap is a high-pass filter. Since there is no resistor (infinitely large), the cutoff frequency is infinitely low, it will pass everything but DC.

There is no current in the diode at steady-state (previously concluded), but the diode also won't let the output voltage go below zero.

High-pass filter, voltage never below zero: conclusion: sine, with bottom of sine at zero.

If you must know what happens for the first cycle(s), you need to analyze in pieces.

For 0 ≤ t ≤ T/2, diode is off.

For T/2 ≤ t ≤ 3T/4, diode is on, cap charges to Vpeak.

For 3T/4 ≤ t, diode is off.

Here is the answer using the simulator:

^{simulate this circuit – Schematic created using CircuitLab}

I modified the diode parameters to make it close to perfect. You can see what I did in this answer. Simple circuit transfer function and output graph

Answer 3

When you assume the diode states than you need to ensure that there are no contradictions in the resulting circuit configuration. By just looking at the I-V characteristics of diode it seems like the ON state is possible but the resulting circuit does not follow KVL.
For the current direction you assumed, the voltage drop across the loop is \$V_1 - V_c > 0\$, since \$V_c < 0\$.
There are no contradictions associated with the OFF state and hence it is the correct state.
EDIT
The circuit diagram on the left shows you the original circuit which is transformed to circuit on the right if diode is assumed to be on. For diode to be ON, the current has to flow in the indicated direction. This implies the capacitor plate connected to node \$V_{out}\$ will be positively charged by the current. Consequently, the voltage drop across the capacitor \$V_c\$, as indicated below, will be positive (I have reversed the polarity of \$V_c\$ from from what you indicated). Now, apply KVL in the A - B - \$V_{out}\$ - D loop: $$0 + V_s + V_c + V_d = 0 \implies V_s + V_c = 0$$. This is a contradiction since both \$V_s\$ and \$V_c\$ are positive as explained before.
But even before solving for these equations, you can see that if you have the circuit on the right the current will flow from the voltage source towards the ground not the other way around, which you indicated. Since diode does not allow such a current, it will be turned off.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 4

It's quite simple: the assumption the diode is in forward mode is incorrect.

Certainly when input goes from zero to peak voltage the diode is off

Correct. No current flows through the capacitor and diode.
Therefore \$V_{out}(t) = V_1(t)\$ for \$ 0 \le t\le T/4 \$.

Both on and off assumptions for the diode is valid when $$T/4\le t\le T/2$$

This statement is incorrect. As we saw above, at \$t = T/4\$ applies: \$V_{out}=V_1(T/4) = V_{peak} \$.
Therefore \$V_D=0-V_{peak}\$, so it is, or better, it stays reversed biased.
In other words, only "the off assumption for the diode" is true.

Note that $$ i_D = -C\frac{d \Big(V_1(t)-Vout(t) \Big)}{dt} = 0 \neq -C_1V_1'$$

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Note that when \$V_{out}(T/4)=0\$ were true, then the remainder of your elaboration is true (I inserted a part):

$$ i_D = -C\frac{d \Big(V_1(t)-Vout(t) \Big)}{dt} = -C_1V_1' \gt 0 \implies V_1'\lt 0$$ which is true because $$V_1' = V_p\omega \cos{\omega t} \ \ \ \ and \ \ \ T/4\le t\le T/2$$

Answer 5

Your problem is that is some inappropriate cases, you used V1 as the voltage across the cap. In fact, isn't V1, it's V1-Vout

Answer 6

Vout will be a sinewave with its negative going troughs peaking at 0V and its positive going peaks peaking at 2*root2*V1 where V1 is the RMS value of the voltage source.

The +ve and -ve signs on the cap are the wrong way around.