All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their implementations. I really would like to see more details about the typical bus widths between the different on chip caches and the upper cache level and the off chip memory; the data bus datapath when Write Through Policy is used; or "Read No allocate" on a Read miss. With the latter policy; how the cache block will be addressed in the main memory, since the fetched word is sent first to the CPU before the entire cache line is copied; in what order the words of the cache line from the main memory will be sent to the cache. I am looking for a good reference or explanation here. Thank you
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\$\begingroup\$ "more details about the typical bus widths ... " there is no answer to that as there are just too many CPUs out there and most manufacturers don't tell you that level of detail. \$\endgroup\$– OldfartCommented Mar 27, 2020 at 11:43
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\$\begingroup\$ @Oldfart . Thank you. I was looking for even one real CPU example reference. What about MIPS? \$\endgroup\$– KM23Commented Mar 27, 2020 at 11:45
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\$\begingroup\$ I don't know the MIPS details. I have worked with a lot of different ARM cores. For performance you can assume details, put them in a spreadsheet and come up wit some accurate performance figures. Then you can then play with the parameters and see what they do. \$\endgroup\$– OldfartCommented Mar 27, 2020 at 11:50
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