In this circuit I am wondering if I really need the n-channel mosfet to control my dual p-channel MOSFET. I think I can drive this straight from the micro. Just want to second opinion before I modify my design.

The CG2_En output can go from 0V to 3.3V. EDIT: The P-Channel MOSFET does not need to switch 20V but it does need to block 20V when it is off. It will only be asked to switch 5V. (Still entertaining answers that require 20V since I have another circuit that will) By default the micro can have its input buffer off presenting somewhat high impedance. Once it wakes it can put out 3.3V. In either state I think the micro would still be subject to a reverse current flow due to the overvoltage. The spec sheet says it can handle an injection current of 1ma (Attiny 1606). @20V with the 47k resistor in place worst case would be (20V-3.3V+0.6V)/47000 = 0.37mA. (I didn't add the 330) Note: This circuit should be initially off. I intend to keep R10 but dump R6 and Q4. Doable?

Original Circuit Circuit

The New circuit New Circuit

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    \$\begingroup\$ The P-Channel MOSFET needs to switch up to 20V. And that's the catch, when making the MCU output high impedance, you'd have 20 V at that output. You would be violating the max ratings of the MCU. Anyway the ESD diodes in the MCU will pull down that voltage so your PMOS will never be off. \$\endgroup\$ Mar 27, 2020 at 15:00
  • \$\begingroup\$ @Bimpelrekkie Sounds answer worthy \$\endgroup\$
    – DKNguyen
    Mar 27, 2020 at 15:02
  • \$\begingroup\$ Sorry, going to edit it. PMOS does not need to switch 20V. only 5V. But needs to block up to 20V when its off. \$\endgroup\$ Mar 27, 2020 at 15:24
  • \$\begingroup\$ The MCU max rating pertains to how much voltage it can switch. From my reading it is OK with any given voltage on the PIN so long as the current into the pin is limited to 1mA. The datasheet gives the equation If VPIN is greater than VDD+0.6V, then a current limiting resistor is required. The positive DC injection current limiting resistor is calculated as R = (Vpin-(VDD+0.6))/ICn. \$\endgroup\$ Mar 27, 2020 at 15:29
  • \$\begingroup\$ Resistors (R5) with no current in them have the same voltage on both sides and the PMOS has a body diode to apply 20V to one end of R5 when the PMOS pair is supposed to be blocking. I am personally not comfortable with relying on clamping of internal diodes. \$\endgroup\$
    – DKNguyen
    Mar 27, 2020 at 15:30

3 Answers 3


The P-Channel MOSFET needs to switch up to 20V.

And that's the catch, when making the MCU output high impedance, you could have 20 V at that MCU's output. You would be violating the maximum ratings of the MCU.

But actually you would not get to 20 V at that output as the ESD protection diodes in the MCU will pull down that voltage (to roughly Vdd + one diode forward voltage or some safe clamping voltage, for example 6 V) so your PMOS will never be off.


Do not operate the MCU pin the way you propose. Applying 20V to a pin that nominally operates from 0 to 3.3V is operating the device outside of recommended guidelines.

Any statement in the data sheet that may say you can inject 1mA through the outputs protection diodes would be of a sort that says you may be able to get away with that momentarily but for normal operating practice it is foolhardy to do this. There is aging of the silicon to consider but even greater concern is the potential for MCU circuit latchup and resulting catastrophic silicon damage that can occur when the current injection happens when the MCU is powering up or down or even in it's off state.

So NO; do not be foolhardy for the sake of a minuscule resistor and a transistor that is at most a SOT-23 package.

  1. PMOS has insufficient max Vgs to not fry when the gate is pulled low (well it does but you are walking a very fine line). Need different PMOS or some kind of zener clamp.
  2. NMOS has insufficient Vgs to achieve rated RDson. Look at transistor datasheets. Pay no attention to the Vgs threshold in digital use. So you need a gate driver for the NMOS but not for gate drive speed. Or use just another NMOS.
  3. R5 required to prevent short circuit while Q4 is conducting and to drain PMOS gate capacitors so they can turn off when Q4 blocking, but balance needs to be found because turning off too slowly could cause PMOS to overheat.
  • \$\begingroup\$ I should have mentioned that the PMOS will never activate under 20V. It just needs to handle 20V on pin6. NMOS doesn't need to achieve any RDson. Its just pulling the gate of the PMOS low, not passing any significant current. The VGSth is 1V to 2.5V right? Dumping R6 not R5. \$\endgroup\$ Mar 27, 2020 at 15:24
  • \$\begingroup\$ @CarlGilbert VGSth is irrelevant for use as a switch. Either use Vgs >= those used to obtain the rated RDson or inspect the I-V curves. \$\endgroup\$
    – DKNguyen
    Mar 27, 2020 at 15:25
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    \$\begingroup\$ @CarlGilbert - the 2N7002 (a common part) will only achieve guaranteed \$R_{DS(on)}\$ with a minimum \$V_{gs}\$ of 5V. See the datasheet. You should look in manufacturers parametric tables for a device that has a guaranteed \$R_{DS(on)}\$ at a \$V_{gs}\$ of 2.5V (quite a lot of them exist). You could alternatively use an NPN bipolar transistor. \$\endgroup\$ Mar 27, 2020 at 15:36
  • \$\begingroup\$ @PeterSmith DKNguyen point taken. If I don't get an explicit RDSon chart I will move on to another NMOS. But if i'm lucky with this circuit I don't even need it here. \$\endgroup\$ Mar 27, 2020 at 15:47

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