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There are bunch of files needed to run an Aldec simulation. What is the minimum set?

Clearly this must include the Verilog/VHDL source, any testbenchs, and a project file. It also needs to include the list of signals from the waveform window.

Specific files suffixes that may or may not be needed are: adf, aws, cfg, dat, ini, log, mgf, order, rlp, set, wsp, wsw.

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The only files I check into my repositories are the VHDL source plus benches and adf files. All the others are automatically created.

I just add the adf files to a new workspace. I always put the VHDL source in a src folder in the same folder as the adf file.

I can't recall what files define the waveform view if you want to preserve that too. Aldec changed their waveform viewer (for the worst IMO) and I've not used it much since as I've not worked in a place lucky enough to own it.

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