Assigning a value to a tri data type variable in Verilog

Suppose there is a 'tri' data type variable A declared in a module m in verilog. A is connected to the output of another module n which is instantiated twice inside m, in both the instances. In one instance the value of A will be 1'bz and in another instance it will be 1'b1. What value will A take? Could you provide reference from any textbook like Samir Palnitkar or any other?

• @KingDuken Verilog does indeed have primitives with three-state outputs. They are the bufif0, bufif1, notif0, and notif1. See section 7.4 of the 2005 IEEE Std 1364. The phrase "three-state" is a characteristic of the primitive rather than a state; the letter Z or z indicates a high-impedance state. Mar 28 '20 at 20:21
• @ElliotAlderson you're right, comment retracted :)
– user103380
Mar 28 '20 at 22:09

In SystemVerilog, wire and tri are aliases for identical net types. Section 6.6.1 Wire and tri nets in the IEEE 1800-2017 LRM explains that the driver with the strongest strength will use its value for resolution. There's no way for a net to have different values when connected through a port, but I assume you meant the driving value in each module. So the result is as defined in table 6-2, which is 1'b1.