# time delay circuit keeping line high

I'd like to create a simple circuit for keeping a line "high" for a few seconds after being triggered high, without any external power.

To specify it in more detail: given three inputs, 3.3V, GND and a processor output line that can be driven high, create a circuit that drives an output line high for 5 seconds after being triggered by the processor output line, even when the 3.3V line goes dead. The timing doesn't need to be exact.

Theoretically, I guess this would be easy by just hooking up a capacitor and a thyristor together. However, suitable thyristors do not seem to be easy to find, and fitting together all the component values seems tricky.

This is also similar to all the power-on / power-off delay circuits, but a little different.

So, I am looking for better ways to do this.

• How long is the trigger? Can't you just switch on the line to resistor and capacitor in parallel, then switch the line to high impedance? Commented Nov 14, 2012 at 22:19
• The trigger is very short, possibly, as switching the output high causes the processor to lose power immediately. Commented Nov 14, 2012 at 22:39

## 1 Answer

Your solution will need to be based upon a capacitor that stores energy to be used by the output circuit to hold up high level pulse. When the trigger pulse arrives it clocks a state to the circuit that is powered from the capacitor power. This could be a flipflop for example. The captured state enables the five second time delay which when it expires will feedback and clear the capture latch. The timing of 5 seconds could be implemented via an R/C circuit, a timer IC or a small pin count microcontroller.

Here is a sample circuit that would do the job using the CMOS version of the 555 chip. (Do not use the old standard NE555 type part. It is not suitable to this application). In this circuit the hold up capacitor is the 220uF part at C1.

The size of the hold up capacitor may have to increase if there is a load placed on the output pin with the 5 second high pulse.

The following picture shows the waveform behavior that you can expect from this circuit. Note that the sloping down high level of the output pulse is caused by the sag of the voltage on C1. The primary load on the CAP is the bias current of the LMC555 timer chip. The two voltage sources driving the simulation circuit are emulating the high level trigger signal from the MCU pin and the resulting shutdown of the 3.3V supply followed by the loss of the MCU output signal.

• Great answer. I would've been even more thrilled about a concrete example which wouldn't use a 555 timer, but you explained it pretty well. Commented Nov 15, 2012 at 14:11
• @Nakedible -- It turns out that the 555 type chip is almost the perfect solution here if you want to go with a non MCU solution. It contains the reference, threshold comparators, trigger logic and the state holding flip-flop. You could build this all with resistors, capacitors and transistors but it would be a rather big glob of components. You could simplify the attached circuit a bit if you were willing to change the trigger from your existing MCU to an output sitting high followed by a narrow pulse going low for a short time. That pulse could feed the TRIG input of the LMC555 directly. Commented Nov 15, 2012 at 17:07