i am designing a basic AES algorithm on verilog, and i need to split a 1828 bits array into 16 parts each one of 8 bits, for example (basic no 128 length example), if i receive in my 8 to 2 splitter module 10111011 i need to generate 4 outputs 10 11 10 11


  • 1
    \$\begingroup\$ You will likely get better answers if you capitalize and have better grammar. Also check you numbers, I don't think you meant 1828 bits. \$\endgroup\$ – Brian Carlton Nov 28 '12 at 0:01

The easiest way, if you don't need to parameterize stuff, would be to use binding, i.e. { }.

For your example using an 8-bit input_sig, you could do this in the following way:

reg [1:0] part0, part1, part2, part3;
always @(input_sig)
   {part3, part2, part1, part0} = input_sig;

That last line essentailly makes one big wire out of each part and assigns input_sig to the new wire bitwise (just like if the new wire was any other 8-bit wire). So if input_sig was 10111011: part3 = 10, part2 = 11, part1 = 10, and part0 = 11.

You can then you can manipulate the parts as you wish. If you do care about parameters, you could use a for loop, but the logic might get a tad complex (at least for my tastes). This solution won't be too cumbersome even for splitting a signal into 16 parts.


You should be able to get away without a for loop if parameterization is the need of the hour.

Something like,

reg [`param1:0] part0, part1, part2, part3;

always @(input_sig) begin
  part0 <= input_signal [`param1:0];
  part1 <= input_signal [2*param1:param1+1]; 
  part2 <= input_signal [3*param1:2*param1+1]; 
  part3 <= input_signal [4*param1:3*param1+1]; 
reg [3:0][`param1:0] part;

always @* 
    for(int i = 0 ; i < 4; i = i + 1)
        part[i] = input_signal[`param*i+:`param]; 
  • \$\begingroup\$ Is that correct Verilog-syntax without a generate-statement? Still upvoting, since it is a correct hint to the OP. \$\endgroup\$ – Andreas Feb 28 '17 at 23:27

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