I found that in
array can only be declared in
And I found that it seems like if can only work in
for loop such as
integer i; reg [3:0] a [0:3]; for (i=0; i<5; i=i+1) a[i] <= i;
what if I want to run in
module testrun( input [7:0] b, input clk, rst, output reg [7:0] c , d, f ); reg state = 0; reg [7:0] a = 5; reg [7:0] e [0:128]; integer i = 0; //reg [7:0] command = 0; always @(posedge clk, posedge rst) begin if (rst) begin c<=0; d<=0; end else begin if (state == 0) begin case (i) i: begin e[i] <= a + 1; f <= a + 1; c <= e[i]; i <= i + 1; a <= a + 1; state <= 1; end endcase end if (state == 1) begin d <= b + b; state <= 0; end end end endmodule
above is the code I test to see if the value of
a + 1 can write into
e[i], then write it into
output c in the next clock.
However, what I get is the
output c is zero all the way. but it shows the expected result of
output d. Means
case actually working just that
array is not working.
What is the problem? Or this can only be sone in SystemVerilog?
By the way, I use
University Program VWF to monitor the result.