# What is input capacitance of pins in IC and what effect does it have?

What is the purpose and the definition of the input capacitance parameter in the datasheet.

I have tried to research about this topic but was only able to find the input capacitance parameter with respect to operational amplifiers only. Even after those research, I was not able to understand the concept of input capacitance with respect to this buffer IC.

Can someone help me with my following queries :

1. What is the definition of input capacitance of a pin in an IC?
2. How is it measured in the first place and is it applicable to all pins in the IC? I am sure, different pins of the IC must have different circuits connected inside. So, the input capacitance of those pins might be different.
3. Is the input capacitance parameter relevant only to supply/signal pins?

4. Why should we care about this parameter of the IC while we design our circuit and how is it relevant?

• As this capacitance is often a few dozen of pF at worst, it affects medium and high speed signals. For low speed signals, it can be ignored (unless it's a very specific application). Mar 31 '20 at 21:51

1) What is the definition of input capacitance of a pin in an IC?

It's the capacitance from that pin to ground or 0 volts.

2) How is it measured in the first place and is it applicable to all Pins in the IC?

It's probably not measured on production items; rather it is essentially always that value unless there is a significant production anomaly on the die. It's applicable to signal inputs.

3) And Why should we care about this parameter of the IC while we design our circuit and how is relevant?

It's a very relevant parameter given that a signal with significant source resistance will have difficulty keeping its rise and fall times short/fast with too much input capacitance.

• On many data sheets, parameters like Cin may be called out as "not measured; guaranteed by design". Mar 31 '20 at 12:08
1. The input capacitance is the capacitance a signal source sees, when you connect the source to that IC pin. This means, if you apply a logic HIGH to that input pin your source has to supply sufficient charge to charge up the capacitance to the desired voltage level.

2. It might be measured directly with something like an LCR meter at the produced item or it might even be just a calculation from the design layout of the chip.

3. Depending on your source impedance it takes time to charge up the input to a specific voltage level. If you know the source impedance as well as the input capacitance you can calculate the exact behaviour of transient events.

The AC drive capability and switching speed of most digital ICs is specified with a specific DC and AC load. So if you want to use this part at its rated speed, you need to know the total capacitance that its driving - interconnects and components. The input capacitance spec of a part helps you with that analysis.

Here's an example from the datasheet for an AC/ACT240. Note that the AC characteristics are specified with a load capacitance Cl of 50 pF.

In simple terms: $$I = C \frac{\Delta V}{\Delta t}.$$

So if you need to change the voltage $$\(\Delta V)\$$ within a certain time $$\(\Delta t)\$$ you can calculate the current $$\(I)\$$ required.

Input signal pins capacitance will include:

1) leadframe capacitance between the metal piecees of the package

2) input capacitance of the bipolar and/or CMOS transistor; for low-noise-amplifiers, this may be picofards.

3) ESD structures designed to rapidly ( < 1 nanosecond) turn on, for voltages only moderately larger than the VDD;

ESD structures can be the major shunting path for high frequency energy, which ruins DATAEYES.

I know of one guy who killed his wife because of the stresses of collapsing revenues, when the ESD diodes were ruining the bit-error-rate of a data-recovery IC, and the historic IC buyers were rejecting the new generation ICs.

summary --- I assume 3pf for input capacitance, whether or not is LNA

now ---- what is the VDD capacitance? On one IC I designed, I plunked down 10pf caps on each end of a place-and-route logic block, in addition to all the Pactive-to-Nsub and the gate-to-bulk parasitics---thus the total >> 200pf.