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I am trying to make a BCD ripple counter that count from 0 to 9 , and I have watched a tutorial on YouTube , I implemented BCD counter as the instructor explained and after the counter reaches the value of 9 it should be cleared in order to begin to count from 0 again.

But my problem is that after the counter reaches 1001 , it clears all flip-flops then make the value of the third flip-flop to one (after 1001 (9) the value will be 0100 (4) not 0000 (0) as I expected).

I don't know what is the cause of the problem, is it due to the clear input ? I simulated the circuit using logisim.

enter image description here

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That circuit is inherently unsafe, which shows again that you should be careful when watching YouTube videos.

The reset is asserted if Q1 and Q3 are high.
But that same reset signal will go away as soon as either Q1 or Q3 is reset. The reset circuit is what we call combinatorial loop.

So in fact what you generate is a reset spike a pulse which is high only for the time the signal takes to go through the loop. That spike might be just long enough to reset all four register but it might not. The only thing is that it most likely will reset is Q1 or Q3.

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  • \$\begingroup\$ Thanks for your declaration . So in the case i suppose there are enough lag in the components in the counter , then it will successfully reset all the flip-flops to be 0 ? \$\endgroup\$ – NAND Mar 31 '20 at 21:05
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    \$\begingroup\$ If you are lucky, yes. but don't turn a circuit like that into a commercial product. If you make enough, some of then will fail. \$\endgroup\$ – Oldfart Apr 1 '20 at 5:41
  • \$\begingroup\$ In order to produce propagation delay, I added 2 inverters after AND gate and seems the circuit works correctly. But the circuit still unreliable, isn't it true ? - Thanks a lot :) \$\endgroup\$ – NAND Apr 2 '20 at 23:28

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