I have been researching how the oscillations across the Drain and Source terminals of a FET occur when it is switched off. I have come across this explanation that it is due to feedback from parasitic capacitance across the Drain to Source terminals of the FET.
This PDF document I found online (Toshiba - Parasitic Oscillation and Ringing of Power MOSFETs) explains it in more detail stating that the reactances across the terminals of the device act as a Colpitts oscillator.
With all that I have read on the subject of Colpitts oscillator I cannot see how the expression for V2 is derived below:
I watched a video online about how a Colpitt's oscillator can be constructed using an Op amp where a gain applied to the input will permit a continuous (non decaying) sinusoidal output provided that it has the resonant frequency.
Here an expression can be determined simply using the voltage divider rule at the output of the Op-Amp with respect to the Impedance network shown on the left.
I then thought to apply the same logic to the circuit shown in the PDF as follows:
My guess was that I could calculate the Impedance due to the parallel RC combination as follows:
(Please excuse my use of photos to explain my logic. I at present only have my phone to work from and entering formulas etc. is difficult.)
Only it doesn't matter how hard I try to resolve this network to find how this expression is calculated, or repackage my own derivation, I can't make sense of this.
Does anybody see something I'm not seeing?