At low-level, registers are the same as a bunch of flip-flops connected by the same clock, so I would think RAM is made of registers.

I've been reading, though, that registers are only in the cpu, which I don't understand.

There are indeed registers in the cpu, ax, bx, etc, but aren't there other registers in memory (RAM) as well?

  • \$\begingroup\$ think the other way around, on chip srams have some number of address lines and some width of data bits, one or a few of them happen to be used to store CPU registers in some processor designs. The rest of the many used in a chip are x number of addressable locations of y width, and they come in a very long list of options 2048 locations of 13 bits wide, 64 locations of 43 bits wide, whatever. \$\endgroup\$
    – old_timer
    Apr 2 '20 at 1:59
  • \$\begingroup\$ Sometimes an sram is used to store cpu registers, other times not depends on the architecture, etc. an x86 being microcoded there is some underlying architecture and that architecture may have registers that might be implemented in an sram depending on that architecture. But some CPU architectures may have each register independently implemented with its own control signals and busses and not use an sram. \$\endgroup\$
    – old_timer
    Apr 2 '20 at 2:02
  • \$\begingroup\$ the idea is that the cell library authors can pack bits and controls into each library more efficiently than the layout author/tools, saving chip realestate, possibly power, etc. So wherever possible/practical you want to use a pre-built library item and not let the tool build it out of discrete parts. \$\endgroup\$
    – old_timer
    Apr 2 '20 at 2:04
  • \$\begingroup\$ or is the question are there other registers as in uart control registers or video display control registers, etc in sram blocks? if that is the question yes where it makes sense definitely. But sometimes it doesnt make sense and in those cases no. Tou often will see fifos and other items in the design that are built around srams. the memory controller on a cpu that handles transactions in flight for the cpu, that is likely going to use an sram in the implementation if it can rather than build it out of discrete items. \$\endgroup\$
    – old_timer
    Apr 2 '20 at 2:08
  • \$\begingroup\$ They aren't called registers on ram \$\endgroup\$
    – tuskiomi
    Apr 3 '20 at 7:22

In a sense, you are correct. The registers in a CPU are the fastest, most expensive type of memory and very similar (possibly even identical but more likely optimized a bit differently) to tightly coupled memory, cache, and on-chip static RAM.

In a very high-level sense, registers are not placed in big blocks on the silicon die like other on-chip static memory (I think, someone correct me if I am wrong). They are placed wherever they are needed by the peripherals and logic they are associated with.

Not dynamic RAM though.

  • \$\begingroup\$ "Not dynamic RAM though" -- travel far enough back in time, and yes, registers were dynamic. I absolutely positively cannot remember which chips used dynamic logic, but there were certainly some in the 1970's and early '80's that had minimum clock speeds. \$\endgroup\$
    – TimWescott
    Apr 1 '20 at 19:47
  • \$\begingroup\$ @TimWescott Hey, for some of it's not so far back! I clearly remember the days of dynamic logic and processors that had a minimum clock frequency. \$\endgroup\$ Apr 1 '20 at 19:49
  • \$\begingroup\$ @TimWescott Why would you use dynamic registers when registers are low density? Wouldn't that just make everything more complicated? \$\endgroup\$
    – DKNguyen
    Apr 1 '20 at 20:08
  • \$\begingroup\$ @ElliotAlderson I do recall that some processors have a minimum clock freqeuncy but it never clicked for me that it might be because of dynamic registers. I remember when I first started reading MCU datasheets that being fully static and able to run at 0Hz was a selling point (never did see one that couldn't do that though) . Now it's a just a given. \$\endgroup\$
    – DKNguyen
    Apr 1 '20 at 20:09
  • \$\begingroup\$ @DKNguyen: Actually, according to the Wikipedia article on dynamic logic it's still a way to go faster with fewer transistors, and some experimentation is on-going. I don't know if it'll ever hit a commercial product, though. \$\endgroup\$
    – TimWescott
    Apr 1 '20 at 20:15

They are similar. It’s a question scale and some implementation details.

Registers tend to be made of clocked D flip-flops. When there’s more than one register in a set, decoders and multiplexers are used to select them. Registers are optimized for speed.

Static RAM arrays are made of latches, which also use decoders and multiplexers to select them. RAM trades some speed for density.

It’s possible to build a RAM with registers - this is sometimes called a register file, and it often shows up as part of a CPU or DSP unit. Some register files even have multiple ports that allow the loading and unloading of more than one data item at a time.

  • \$\begingroup\$ Why the different usage between D flip-flops and latches? Isn't all on-chip memory synchronous? \$\endgroup\$
    – DKNguyen
    Apr 1 '20 at 18:59
  • \$\begingroup\$ Not necessarily. For the RAM block there will be local pulse timing to complete a write cycle on a RAM - think async SRAM chips of old that had separate R and W signals. Fundamentally, this gated a latch open for write. This has lower latency than the write were pipelined, as it would be were it to use D flops. Also, a latch cell is fewer transistors than a D flop. \$\endgroup\$ Apr 1 '20 at 19:05
  • \$\begingroup\$ Well, I understand about asynchronous SRAM but I always thought those were only ever external. I had always assumed all on-chip memory was synchronous. Fewer signals for a lot of memory cells makes sense though. \$\endgroup\$
    – DKNguyen
    Apr 1 '20 at 19:06
  • \$\begingroup\$ It’s synchronous if it’s pipelined - it’s an option to trade latency for clock speed. But internally the RAM block still uses latches for density instead of D ff’s as for registers. \$\endgroup\$ Apr 1 '20 at 19:09

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