I'm analyzing the layout of a circuit by parsing the LEF and DEF files with PyParsing (Python). I parsed everything, no problem in this part. I also have on the side the netlist of the circuit.
My goal is to know the position of the drains of transistors, its mos type (n or p) and its net name.
The problem is that for in/out pins the LEF gives the name of the pin, but for internal nets, they are all in the OBS section of the LEF file and I can't know which transistor refers to a specific net. I'm missing some file that describes all the nets in the layout? I can't use GDS for this problem.
Electrical netlist of a NAND gate
.subckt NAND ina inb out vdd vdd 0 DC 1 M1 out ina vdd vdd PMOS L=1 W=20 M2 out inb vdd vdd PMOS L=1 W=20 M3 out ina n1 0 NMOS L=1 W=20 M4 n1 inb 0 0 NMOS L=1 W=10 .ends NAND
Part of a LEF netlist of a NAND gate
MACRO NAND PIN out DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER CONTACT ; POLYGON 2.088 0.262 2.128 0.262 2.128 0.302 2.088 0.302 ; END END out
Here we know where PIN out is located due to its contact to the active.
However, the other internal drain net (n1) is described as follows:
OBS LAYER CONTACT ; POLYGON 0.048 0.223 0.088 0.223 0.088 0.263 0.048 0.263 ;
For the NAND gate in which has only one internal drain net we know its location, but for more complex circuits, we can't distinguish which LAYER CONTACT corresponds to the drain contact of a specific net.