Is it possible to have two clock signals driving a JK toggling flip flop, in which both signals are connected by a XOr gate so that the flip flop only works on either edge of either clock? If possible, then there are also two sequences for how the clock inputs will go. Assume that the clock is positive edge triggered.enter image description here

For Sequence A, Phase 1 is when the clock is driven to 0 by the two low inputs. In Phase 2, the clock is driven 1 by Input 1, after which a desired flip flop output is obtained. Afterwards, in Phase 3, the clock goes back to 0 when the input combination is "11" due to the XOr gate, where the Q output will stay the same. In Phase 4, now the combination is "01" after "11", the clock is back on. Despite this, I wish to keep the output as obtained in Phases 2 and 3.

On the other hand, for Sequence B, Input 2 going high first in Phase 2 will generate a desired Q output, which is different than the one obtained in the first sequence. Similarily as in the first sequence, "11" combination will turn the clock off due to the XOr Gate. Finally, at "10" I wish to keep the same Q output as the 2nd and 3rd Phases.

The Output "Q" is supposed to be like the following, assuming that the flip flop is initially at RESET:enter image description here

It might be confusing, but is any of this possible? Thank you.

  • 1
    \$\begingroup\$ You've drawn the input waveforms. It would be less confusing if you draw your desired output waveforms as well. Is this a 'first contestant to press the button' indicator? \$\endgroup\$ – Neil_UK Apr 2 '20 at 5:12
  • \$\begingroup\$ @Neil_UK Thanks for the note. I have modified the post to contain the Q output I wish to have from both sequences. Also, it isn't the indicator you've mentioned. \$\endgroup\$ – Zelreedy Apr 2 '20 at 6:19
  • \$\begingroup\$ You've only drawn one Q output, how is that different from the first? Draw an output under sequence A, draw another output under sequence B. You might find you answer your own question once you've been forced to show us precisely what you want. Input 2 going high first in Phase 2 will generate a desired Q output, which is different than the one obtained in the first sequence. \$\endgroup\$ – Neil_UK Apr 2 '20 at 7:49
  • \$\begingroup\$ @Neil_UK The Q output for Sequence A from the waveform I added is 1, while the Q output for Sequence B is 0. I just combined both sequences for clarity on how they are different. Sequence A generates a high, while Sequence B generates a low. \$\endgroup\$ – Zelreedy Apr 2 '20 at 8:27
  • \$\begingroup\$ Don't paint word pictures, DRAW A DIAGRAM, showing each sequence and its results, in time alignment. It's an important skill that all engineers have to learn, and as I said, the answer may pop out at you as you are forced to put on paper exactly what you want. 'I just combined both sequences for clarity'? What would the next sentence read like if I combined the first half with the second half 'for clarity'? Voting to close. \$\endgroup\$ – Neil_UK Apr 2 '20 at 10:02

Yes, you can do it with a J-K flip-flop. Look at the logic table. You can play with it in different manners. Maybe you won't even need a XOR gate. But you may need an OR gate to connect the two clock lines to a single CLK input. If the clock is also feeding the inputs, then you must add a small RC delay circuit (1Kohm + 100pF is enough) to make sure the signal arrives at the J and/or K inputs before it arrives at the CLK input.

Also make sure that the two clock pulses are distinct. Not rising at too close interval or practically at the same time. The interval must at least twice the total propagation delay of the whole component chain. 1µs should be ok.


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